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Thu, 10 Dec 2020 17:13:46 +0000 From: Tom Lendacky To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org Cc: Paolo Bonzini , Jim Mattson , Joerg Roedel , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Borislav Petkov , Ingo Molnar , Thomas Gleixner , Brijesh Singh Subject: [PATCH v5 23/34] KVM: SVM: Add support for CR8 write traps for an SEV-ES guest Date: Thu, 10 Dec 2020 11:09:58 -0600 Message-Id: <5a01033f4c8b3106ca9374b7cadf8e33da852df1.1607620209.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: CH2PR07CA0033.namprd07.prod.outlook.com (2603:10b6:610:20::46) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by CH2PR07CA0033.namprd07.prod.outlook.com (2603:10b6:610:20::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?A/bP3zoIbW4QYU59JhDLli0ex2722GeF0K5cM4fMgVV2S0GfM9yJJZFINtSH?= =?us-ascii?Q?SEbPZZPMo7aq5QceX70REWXQTcDszGwpB/B9Jymj0SIDGgqbVxkOazPPqPxB?= =?us-ascii?Q?ofPYHBr/IA+t0j9xqWLibIjM6UdMXVqNblffTTp6wLGSYWkU+5vYm/yp4PRo?= =?us-ascii?Q?2bQaVFvjnj9Z+oysiU1BUg9d1wMVfNUSTolvraBgFJWaSVtfL7TKHRtlT7Y7?= =?us-ascii?Q?nf+Es9HxrJpLCWcuENGqGYR7i8iH1dX2uLhKZsnYjP+I8BEh9fiYLX6ZDZGq?= =?us-ascii?Q?WJcvR1VkdOxxlt2M0Aql6nqGksj9XFyj2YK1C5EFayTe196FgyR1uO8CzNId?= =?us-ascii?Q?cq7OOxwknD3CTT9GYThS7ewBL2t17Vr/F1R0xkd6wx9PIaVrVk8IRjckKH+E?= =?us-ascii?Q?iwShAolPTDihSDj2wFKXIFvs687h61sYwNwkAsPj9tEwerG2JIR2SE3mlMxy?= =?us-ascii?Q?oezw7fdT8Zjg+5x5WYopTF6gSQFtby0jJhIAf2CGpNTL2eGGfRTKXo6L0LnT?= =?us-ascii?Q?+6KnnMBjV93CTdmt9d5cRlNsJ36putgYPSazTjhnL7anKJgbSfQHXJHDr33Q?= =?us-ascii?Q?GjBFSfYI4DB/d31DDeXTjveR0/LO1MVwyTHcbk0dcmpqXbFEdX0e+4sOuh2b?= =?us-ascii?Q?WW5lwztu4zb0jcCkNBiughlSlN7QizxGTSNrM2kMYGw12N+8vRvYKw0qLX5O?= =?us-ascii?Q?Xs/xAcYBbdeq6D1wob99QY2eMF42etesilKhAMQ2BJ4cNCgNi6pcH0iz8Tol?= =?us-ascii?Q?0I8pppaS33gh/miHoECOC0M9MHMBGRNbUlyqLAfHUZg1d3WbHVzECLX/miAD?= =?us-ascii?Q?tsZOV8KWWI23Z2hTAIM5MZarnd47mWE4s3MqK6uqW2D2BzLEQaX9//7WZJ3o?= =?us-ascii?Q?R/5X6SJQvrBqARaoItzDywJiGrvrfG1lp0RwOFYHxS3UdD6KuLMmjCtiKLxP?= =?us-ascii?Q?jH3u3tpy6Rh7ay8i7va/vqLnLDFyyDNKcYyqMzsJqcvzUFRd8rUiIX87zP3W?= =?us-ascii?Q?t03I?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthSource: CY4PR12MB1352.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2020 17:13:46.2982 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-Network-Message-Id: f669bd3b-7f06-4256-e48d-08d89d2ef43a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KP0MBNa2w9Lr+CMvI5dr6mJ9RHmMl5B95CC0mBwk6la8OZBC92HzXQw9eVnh5vRWj6hZdhXrtR3rUYz/lS6iPg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0149 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tom Lendacky For SEV-ES guests, the interception of control register write access is not recommended. Control register interception occurs prior to the control register being modified and the hypervisor is unable to modify the control register itself because the register is located in the encrypted register state. SEV-ES guests introduce new control register write traps. These traps provide intercept support of a control register write after the control register has been modified. The new control register value is provided in the VMCB EXITINFO1 field, allowing the hypervisor to track the setting of the guest control registers. Add support to track the value of the guest CR8 register using the control register write trap so that the hypervisor understands the guest operating mode. Signed-off-by: Tom Lendacky --- arch/x86/include/uapi/asm/svm.h | 1 + arch/x86/kvm/svm/svm.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index c4152689ea93..554f75fe013c 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -204,6 +204,7 @@ { SVM_EXIT_EFER_WRITE_TRAP, "write_efer_trap" }, \ { SVM_EXIT_CR0_WRITE_TRAP, "write_cr0_trap" }, \ { SVM_EXIT_CR4_WRITE_TRAP, "write_cr4_trap" }, \ + { SVM_EXIT_CR8_WRITE_TRAP, "write_cr8_trap" }, \ { SVM_EXIT_INVPCID, "invpcid" }, \ { SVM_EXIT_NPF, "npf" }, \ { SVM_EXIT_AVIC_INCOMPLETE_IPI, "avic_incomplete_ipi" }, \ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e15e9e15defd..3fb1703f32f8 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2475,6 +2475,7 @@ static int cr_trap(struct vcpu_svm *svm) struct kvm_vcpu *vcpu = &svm->vcpu; unsigned long old_value, new_value; unsigned int cr; + int ret = 0; new_value = (unsigned long)svm->vmcb->control.exit_info_1; @@ -2492,13 +2493,16 @@ static int cr_trap(struct vcpu_svm *svm) kvm_post_set_cr4(vcpu, old_value, new_value); break; + case 8: + ret = kvm_set_cr8(&svm->vcpu, new_value); + break; default: WARN(1, "unhandled CR%d write trap", cr); kvm_queue_exception(vcpu, UD_VECTOR); return 1; } - return kvm_complete_insn_gp(vcpu, 0); + return kvm_complete_insn_gp(vcpu, ret); } static int dr_interception(struct vcpu_svm *svm) @@ -3084,6 +3088,7 @@ static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap, [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap, [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap, + [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap, [SVM_EXIT_INVPCID] = invpcid_interception, [SVM_EXIT_NPF] = npf_interception, [SVM_EXIT_RSM] = rsm_interception, -- 2.28.0