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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b486970b37bsm1681982366b.53.2025.10.08.04.51.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Oct 2025 04:51:20 -0700 (PDT) Message-ID: <5a027440-8720-4df9-a793-5ac3a624ef60@oss.qualcomm.com> Date: Wed, 8 Oct 2025 13:51:16 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/17] drm/msm/a6xx: Rebase GMU register offsets To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> <20250930-kaana-gpu-support-v1-10-73530b0700ed@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250930-kaana-gpu-support-v1-10-73530b0700ed@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAwMSBTYWx0ZWRfX1GM4eoe5mW2S aPBxUXSSzPMU/AlXSV5RCDwGSVMYmK74v96YTjlYTvJuJG27W1jEzyyl2b+jqdmLAcMdLPo9h/h XZ4nWkhMZ8xDXfSy/Muzz7r/eSizyBvKMYRVgjSW3avGrGA82PEZ0RhKXVe9Nl+TyxMrmoLh2mg 3GJ2pbO/al462zWom9S9Z7aU41pngUSKWIy9zri0jmHCGbn//lkPeKjV3jh77msAUqqze+nszdq JsAwBkGKaQRdN6cq9a7SNTJb6/ui958K80BfCnioASEUPxPp177uSZpFtH+gFCesTui4b5fjLth BCfK6poxBPcvHpsJo/8lBl3JEo//eoyJ6h9JwZH8BjVMY8w+ObBo/SgFZpE7NlwoY+fZbIhNP62 GyPqG7zhO9dGRBpuZV6C98H4tJMh9A== X-Proofpoint-GUID: ED8C3fNOf3FXouCR6N5b0cEDC-MbKQkt X-Proofpoint-ORIG-GUID: ED8C3fNOf3FXouCR6N5b0cEDC-MbKQkt X-Authority-Analysis: v=2.4 cv=EqnfbCcA c=1 sm=1 tr=0 ts=68e6503a cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=abYYEtMJDLCSMuBgjaEA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-08_03,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040001 On 9/30/25 7:48 AM, Akhil P Oommen wrote: > GMU registers are always at a fixed offset from the GPU base address, > a consistency maintained at least within a given architecture generation. > In A8x family, the base address of the GMU has changed, but the offsets > of the gmu registers remain largely the same. To enable reuse of the gmu > code for A8x chipsets, update the gmu register offsets to be relative > to the GPU's base address instead of GMU's. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 44 +++- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 20 +- > drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 248 +++++++++++----------- > 3 files changed, 172 insertions(+), 140 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index fc717c9474ca5bdd386a8e4e19f43abce10ce591..72d64eb10ca931ee90c91f7e004771cf6d7997a4 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -585,14 +585,14 @@ static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) > } > > static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, > - const char *name); > + const char *name, resource_size_t *start); Maybe you can keep this offset variant and switch to a simple devm_platform_get_and_ioremap_resource() for others (also letting us get rid of a number of iounmap() calls) [...] > + /* The 'offset' is based on GPU's start address. Adjust it */ That's what an offset is, no? ;) I think we can drop this comment or move it above the #define Konrad