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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b7339a7078dsm105318066b.6.2025.11.12.05.34.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 05:34:26 -0800 (PST) Message-ID: <5a1aaf4a-c5d5-42e1-9044-d12a6c231904@oss.qualcomm.com> Date: Wed, 12 Nov 2025 14:34:24 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs To: Bibek Kumar Patro , Enric Balletbo i Serra Cc: robdclark@gmail.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, jsnitsel@redhat.com, robh@kernel.org, krzysztof.kozlowski@linaro.org, quic_c_gdjako@quicinc.com, dmitry.baryshkov@linaro.org, iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Maxime Ripard , Eric Chanudet , charan.kalla@oss.qualcomm.com References: <20241212151402.159102-1-quic_bibekkum@quicinc.com> <33826089-54b5-47bc-8a5b-6004c7a276b8@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <33826089-54b5-47bc-8a5b-6004c7a276b8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDExMSBTYWx0ZWRfX4uZig34jkzo7 2YbURgaadFfg3fyUD2Cf5gX/46wmu2Q7LXYtLaE50PsqKamQ3VUKWe+DoAIyTZFiM22wAgZvju/ D6f/Y/HGhScP3VynChKkAYGj4gRmqfpPYObXRE0KsNCN4Blq0C+fXSvLZ8qpAyq5ogfPggDSRZA h5ohUcmY95haGn5LpzzGiAfTxOoLpa7kkVDGprSX13CFMN96arRtPDl5NTz7QFLxfHBPrR3JdV/ 6M1zJCQxJtqTrpvXUoxtfp1+i2LOOMQen5sozaEeIztkKlulr359DfCIyEvMtM2QwfB72eOQivo PKxpnelKLWp2LrrJJqOkAYPjtWkrtzdDN1PivaBG9UdFGvTPR2X11+WWukj4+pfAvhJSo0wPmLT 57fG494IbuWZRDDBP3UwT1alcpdfXw== X-Proofpoint-GUID: _MrMCjIP3-rNwWwJYSCEw23wCXN54h5Q X-Authority-Analysis: v=2.4 cv=bbBmkePB c=1 sm=1 tr=0 ts=69148f66 cx=c_pps a=zPxD6eHSjdtQ/OcAcrOFGw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=QyXUC8HyAAAA:8 a=i3X5FwGiAAAA:8 a=EUspDBNiAAAA:8 a=SKrgUew0zp_WtuwtRiYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=y8BKWJGFn5sdPF1Y92-H:22 a=TjNXssC_j7lpFel5tvFf:22 a=mmqRlSCDY2ywfjPLJ4af:22 X-Proofpoint-ORIG-GUID: _MrMCjIP3-rNwWwJYSCEw23wCXN54h5Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120111 On 11/12/25 9:45 AM, Bibek Kumar Patro wrote: > > > On 11/7/2025 2:58 PM, Enric Balletbo i Serra wrote: >> On Thu, Dec 12, 2024 at 4:14 PM Bibek Kumar Patro >> wrote: >>> >>> This patch series consist of six parts and covers the following: >>> >>> 1. Provide option to re-enable context caching to retain prefetcher >>>     settings during reset and runtime suspend. >>> >>> 2. Remove cfg inside qcom_smmu structure and replace it with single >>>     pointer to qcom_smmu_match_data avoiding replication of multiple >>>     members from same. >>> >>> 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface. >>> >>> 4. Introduce intital set of driver changes to implement ACTLR register >>>     for custom prefetcher settings in Qualcomm SoCs. >>> >>> 5. Add ACTLR data and support for qcom_smmu_500. >>> >>> Changes in v18 from v17_RESEND: >>>   - 1/5 : No changes >>>   - 2/5 : No changes - reviewed-by tags collected >>>   - 3/5 : Addition of >>>     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend() >>>     around register access of PRR related private interfaces >>>     as discussed in v17_RESEND. >>>   - 4/5, 5/5 : No changes - reviewed-by tags collected >>>   Link to v17_RESEND: >>>   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/ >>> >>> Resend of v17: >>>   Addition of minor fix of the build warning reported by kernel test robot [1] by powerpc_random config [2]. >>>   [1]:https://lore.kernel.org/all/202411140748.6mcFdJdO-lkp@intel.com/#t >>>   [2]:https://download.01.org/0day-ci/archive/20241114/202411140748.6mcFdJdO-lkp@intel.com/config >>> >>> Changes in v17 from v16: >>>   Tags provided earlier not collected yet on patch 1/5, 3/5, 4/5, 5/5 >>>   due to the following revisions: >>>   - 1/5 : Move the CPRE workaround out of qualcomm specific logic and gate with config >>>           , update the silicon-errata.rst file >>>   - 2/5 : No changes - reviewed-by tags collected >>>   - 3/5 : Move the compatible check before assignment of callback as suggested. >>>   - 4/5 : Add the actlr setting for *adreno variant* of MMU-500 as well. >>>   - 5/5 : Due to changes in 1/5, minor refactoring had to be done before adding table. >>>   Link to v16: >>>   https://lore.kernel.org/all/20241008125410.3422512-1-quic_bibekkum@quicinc.com/ >>> >>> Changes in v16 from v15: >>>   - Incorporate Dimitry's suggestion on patch 4/5 to use dev_dbg instead of dev_notice. >>>   - Fix kernel test robot warning [1] coming for 32bit architecture configuration. >>>   - Updatingthe tags >>>   [1]: https://lore.kernel.org/all/202409230343.Q8KnYl2w-lkp@intel.com/ >>>   Link to v15: >>>   https://lore.kernel.org/all/20240920155813.3434021-1-quic_bibekkum@quicinc.com/ >>> >>> Changes in v15 from v14: >>>   - As discussed with Robin and Dmitry modify the actlr table and logic to use >>>     compatible string instead of sid, mask for device matching which is >>>     similar to qcom_smmu_client_of_match mechanism. >>>   - Expand the comment in qcom_smmu500_reset to document reason why CPRE bit is re-enabled again >>>     after arm_mmu500_reset resets the bit. >>>   - Rearrange the series in order to keep prefetch setting patches in the end. >>>   Link to v14: >>>   https://lore.kernel.org/all/20240816174259.2056829-1-quic_bibekkum@quicinc.com/ >>> >> >> Hi all, >> >> I've been looking at the evolution of the Qualcomm SMMU driver >> (arm-smmu-qcom.c) and had a question about the design change for >> configuring the SMMU_CB_ACTLR register. >> >> It appears there are two different approaches: >> >> 1. The "SID" Approach (Older): In some versions, a driver would use a >> large, platform-specific struct (e.g., sa8775p_apps_actlr_cfg) that >> maps individual Stream IDs (SIDs) to specific ACTLR values. This >> allowed for very granular, per-SID tuning. For example, a device with >> 10 SIDs could have a specific setting for just one (0x2141), while the >> others used a default. >> >> 2. The "Compatible String" Approach (Newer/Upstream): The current >> upstream driver appears to use a client_match array (an of_device_id >> list) in qcom_smmu_init_context. This maps a device's compatible >> string to a single ACTLR value, which is then written to the device's >> assigned Context Bank. >> >> I want to make sure I understand the implications of this new, simpler >> approach, as it seems to introduce a trade-off where granularity is >> lost: >> >> Multiple SIDs, One Device: A single device that uses many SIDs in the >> device tree (e.g., the video codec, which might list 0x2141, 0x25C1, >> 0x2161, etc.) will now have one ACTLR setting applied to the Context >> Bank that serves all of those SIDs, even if the old SID-based list >> only specified a setting for one of them. >> >> Am I correct in this analysis? I'm assuming this was an intentional >> design choice to simplify the driver, based on the assumption that all >> SIDs for a single device (and all devices with the same compatible) >> can share the same ACTLR tuning. >> > > Hi Eric, > > If a device has multiple SIDs, all serving the same functionality and grouped under the same "iommus" field, for example: > > iommus = <&apps_smmu, 0x2141, 0x0>, >           <&apps_smmu, 0x25c1, 0x0>, >           <&apps_smmu, 0x2161, 0x0>; > > In this case, all the SIDs will be associated with the same context bank. Even if the three SIDs have different ACTLR settings, since SMMU_CB_ACTLR is per CB setting, all SIDs attached to that bank will share the same ACTLR configuration. This is why we designed it to be "per device / per compatible". Does that suggest the settings may be slightly suboptimal? There's some work being done to allow more granular association of the passed SIDs: https://lore.kernel.org/linux-arm-msm/20250928171718.436440-1-charan.kalla@oss.qualcomm.com/ Konrad