From: Chaitanya Kulkarni <chaitanyak@nvidia.com>
To: Michael Kelley <mikelley@microsoft.com>
Cc: "caroline.subramoney@microsoft.com"
<caroline.subramoney@microsoft.com>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"axboe@fb.com" <axboe@fb.com>,
"riwurd@microsoft.com" <riwurd@microsoft.com>,
"nathan.obr@microsoft.com" <nathan.obr@microsoft.com>,
"sagi@grimberg.me" <sagi@grimberg.me>,
"kbusch@kernel.org" <kbusch@kernel.org>,
"hch@lst.de" <hch@lst.de>
Subject: Re: [PATCH v4 1/1] nvme: handle persistent internal error AER from NVMe controller
Date: Thu, 9 Jun 2022 00:28:10 +0000 [thread overview]
Message-ID: <5a27e5a5-74eb-6c65-eb68-c655c3b5ae6e@nvidia.com> (raw)
In-Reply-To: <0e57d8c2-9a30-f15e-dc38-da397ac81c34@nvidia.com>
On 6/8/22 17:22, Chaitanya Kulkarni wrote:
> On 6/8/22 11:52, Michael Kelley wrote:
>> In the NVM Express Revision 1.4 spec, Figure 145 describes possible
>> values for an AER with event type "Error" (value 000b). For a
>> Persistent Internal Error (value 03h), the host should perform a
>> controller reset.
>>
>> Add support for this error using code that already exists for
>> doing a controller reset. As part of this support, introduce
>> two utility functions for parsing the AER type and subtype.
>>
>> This new support was tested in a lab environment where we can
>> generate the persistent internal error on demand, and observe
>> both the Linux side and NVMe controller side to see that the
>> controller reset has been done.
>>
>>
Can you please clarify that which transports you have tested
such as RDMA, TCP, and PCIe ?
-ck
next prev parent reply other threads:[~2022-06-09 0:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-08 18:52 Michael Kelley
2022-06-09 0:22 ` Chaitanya Kulkarni
2022-06-09 0:28 ` Chaitanya Kulkarni [this message]
2022-06-09 1:30 ` Michael Kelley (LINUX)
2022-06-09 5:06 ` Chaitanya Kulkarni
2022-06-13 18:08 ` Christoph Hellwig
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