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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-343e06fe537sm21110853a91.2.2025.11.18.01.35.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Nov 2025 01:35:15 -0800 (PST) Message-ID: <5a308d21-d463-4d6f-b5d3-95a0c2ede2c1@oss.qualcomm.com> Date: Tue, 18 Nov 2025 17:35:09 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] wifi: ath12k: fix endianness handling for SRNG ring pointer accesses To: Alexander Wilhelm , Jeff Johnson Cc: linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251118072123.19355-1-alexander.wilhelm@westermo.com> From: Baochen Qiang Content-Language: en-US In-Reply-To: <20251118072123.19355-1-alexander.wilhelm@westermo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: B58uIAr8uutf4O5wRYrrmB442jS6ygrs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA3NSBTYWx0ZWRfX1GId9i3d7A4f imd17rRd8hmUBRL1NuFkOhGvWOe48iJMpIGa08xkiZuTxrlQxEzDjbcPIyTR8l0DV48/8J62HqY kUqNmSR+gZ/jZzy9RyrSNUxYmz/HbtAwa6b6DY7DbabCpucI4iwidfJjUuRmT1yRHiRUoc5TxTT r7LOu0kj/NL0mF4ABVT61MfdZQUk4sbDzt5OeqptnxhxqasVW6GcXY5AeLahYksgyWIkvMKRden skXh9SUgqvjXk1x6hK7P3bIZ4qG8q19BhG2ZP7hJvh43apqdiI+xLQ96P/z2e71qENgvTYn674o vvBWoqOgvqgFKJLuHmdkOVzTNwaPlwgvHfmvjUxx63Mbk7CT5Zp1ukiGvb7kxwGucpfRPWgkYRa sjjkm8zyQ1Yb9qYAuLfS9BzWayDWnw== X-Authority-Analysis: v=2.4 cv=cs+WUl4i c=1 sm=1 tr=0 ts=691c3dd5 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=N9GNhs4bAAAA:8 a=Sty9O8k4TDZ2vQ3Klh0A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=PZhj9NlD-CKO8hVp7yCs:22 X-Proofpoint-ORIG-GUID: B58uIAr8uutf4O5wRYrrmB442jS6ygrs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180075 On 11/18/2025 3:21 PM, Alexander Wilhelm wrote: > The SRNG head and tail ring pointers are stored in device memory as > little-endian values. On big-endian systems, direct dereferencing of these > pointers leads to incorrect values being read or written, causing ring > management issues and potentially breaking data flow. > > This patch ensures all accesses to SRNG ring pointers use the appropriate > endianness conversions. This affects both read and write paths for source > and destination rings, as well as debug output. The changes guarantee > correct operation on both little- and big-endian architectures. > > Signed-off-by: Alexander Wilhelm > --- > drivers/net/wireless/ath/ath12k/hal.c | 35 +++++++++++++++------------ > 1 file changed, 20 insertions(+), 15 deletions(-) > > diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c > index 6406fcf5d69f..bd4d1de9eb1a 100644 > --- a/drivers/net/wireless/ath/ath12k/hal.c > +++ b/drivers/net/wireless/ath/ath12k/hal.c > @@ -2007,7 +2007,7 @@ int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, > tp = srng->u.dst_ring.tp; > > if (sync_hw_ptr) { > - hp = *srng->u.dst_ring.hp_addr; > + hp = le32_to_cpu(*srng->u.dst_ring.hp_addr); should we also need to change its type to '__le32 *'? > srng->u.dst_ring.cached_hp = hp; > } else { > hp = srng->u.dst_ring.cached_hp; > @@ -2030,7 +2030,7 @@ int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng, > hp = srng->u.src_ring.hp; > > if (sync_hw_ptr) { > - tp = *srng->u.src_ring.tp_addr; > + tp = le32_to_cpu(*srng->u.src_ring.tp_addr); > srng->u.src_ring.cached_tp = tp; > } else { > tp = srng->u.src_ring.cached_tp; > @@ -2149,9 +2149,9 @@ void ath12k_hal_srng_access_begin(struct ath12k_base *ab, struct hal_srng *srng) > > if (srng->ring_dir == HAL_SRNG_DIR_SRC) { > srng->u.src_ring.cached_tp = > - *(volatile u32 *)srng->u.src_ring.tp_addr; > + le32_to_cpu(*(volatile u32 *)srng->u.src_ring.tp_addr); > } else { > - hp = READ_ONCE(*srng->u.dst_ring.hp_addr); > + hp = le32_to_cpu(READ_ONCE(*srng->u.dst_ring.hp_addr)); > > if (hp != srng->u.dst_ring.cached_hp) { > srng->u.dst_ring.cached_hp = hp; > @@ -2175,25 +2175,28 @@ void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng) > * hence written to a shared memory location that is read by FW > */ > if (srng->ring_dir == HAL_SRNG_DIR_SRC) { > - srng->u.src_ring.last_tp = > - *(volatile u32 *)srng->u.src_ring.tp_addr; > + srng->u.src_ring.last_tp = le32_to_cpu( > + *(volatile u32 *)srng->u.src_ring.tp_addr); > /* Make sure descriptor is written before updating the > * head pointer. > */ > dma_wmb(); > - WRITE_ONCE(*srng->u.src_ring.hp_addr, srng->u.src_ring.hp); > + WRITE_ONCE(*srng->u.src_ring.hp_addr, > + cpu_to_le32(srng->u.src_ring.hp)); > } else { > - srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; > + srng->u.dst_ring.last_hp = > + le32_to_cpu(*srng->u.dst_ring.hp_addr); > /* Make sure descriptor is read before updating the > * tail pointer. > */ > dma_mb(); > - WRITE_ONCE(*srng->u.dst_ring.tp_addr, srng->u.dst_ring.tp); > + WRITE_ONCE(*srng->u.dst_ring.tp_addr, > + cpu_to_le32(srng->u.dst_ring.tp)); > } > } else { > if (srng->ring_dir == HAL_SRNG_DIR_SRC) { > - srng->u.src_ring.last_tp = > - *(volatile u32 *)srng->u.src_ring.tp_addr; > + srng->u.src_ring.last_tp = le32_to_cpu( > + *(volatile u32 *)srng->u.src_ring.tp_addr); > /* Assume implementation use an MMIO write accessor > * which has the required wmb() so that the descriptor > * is written before the updating the head pointer. > @@ -2203,7 +2206,8 @@ void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng) > (unsigned long)ab->mem, > srng->u.src_ring.hp); > } else { > - srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; > + srng->u.dst_ring.last_hp = > + le32_to_cpu(*srng->u.dst_ring.hp_addr); > /* Make sure descriptor is read before updating the > * tail pointer. > */ > @@ -2547,7 +2551,7 @@ void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, > * HP only when then ring isn't' empty. > */ > if (srng->ring_dir == HAL_SRNG_DIR_SRC && > - *srng->u.src_ring.tp_addr != srng->u.src_ring.hp) > + le32_to_cpu(*srng->u.src_ring.tp_addr) != srng->u.src_ring.hp) > ath12k_hal_srng_access_end(ab, srng); > } > > @@ -2648,14 +2652,15 @@ void ath12k_hal_dump_srng_stats(struct ath12k_base *ab) > "src srng id %u hp %u, reap_hp %u, cur tp %u, cached tp %u last tp %u napi processed before %ums\n", > srng->ring_id, srng->u.src_ring.hp, > srng->u.src_ring.reap_hp, > - *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp, > + __le32_to_cpu(*srng->u.src_ring.tp_addr), > + srng->u.src_ring.cached_tp, > srng->u.src_ring.last_tp, > jiffies_to_msecs(jiffies - srng->timestamp)); > else if (srng->ring_dir == HAL_SRNG_DIR_DST) > ath12k_err(ab, > "dst srng id %u tp %u, cur hp %u, cached hp %u last hp %u napi processed before %ums\n", > srng->ring_id, srng->u.dst_ring.tp, > - *srng->u.dst_ring.hp_addr, > + __le32_to_cpu(*srng->u.dst_ring.hp_addr), why __le32_to_cpu() only in logging, while le32_to_cpu() elsewhere? > srng->u.dst_ring.cached_hp, > srng->u.dst_ring.last_hp, > jiffies_to_msecs(jiffies - srng->timestamp)); > > base-commit: be83ff7549057d184b693a85cafc10fbd520f3d7