From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout06.his.huawei.com (canpmsgout06.his.huawei.com [113.46.200.221]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 433F63B27F4 for ; Fri, 7 Aug 2026 07:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.221 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786087300; cv=none; b=FkEw49JL8iUe8eolDVmY+sMztc9N4Cwn8CnJqL5U8ibMwKB/aQIX3aQBiXwdm3Oyvywpx2R1B4V5xoJIPZGrr9e9hLnCjNpWpGemSQzfmTe/+4XXnJkDUEICEGOGg6raIFoZo5/Ton9sbn+jL+eVbZ/On96uNkSLU0hiDer5jr8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786087300; c=relaxed/simple; bh=I0ICxerVzPoDkTiWwuxm/0MrzMnKGsfpGn+yinW5hoo=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=GiQE4PwfHli0pPcbW1OncJpj72BNOrW/Tgl/XncTFXghFFswt+pNqx5fSWNCgWr8AMoj6aNXoy9noAK+whN0ECkIUZR/WPl6BGG9PUDTzfKTODG4PLGpb3/Yjriv95o2ltUza1OtzzTfRxicOG3Q39GV4LWS2EhIZbR+IG8bnAo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=Ke0qftcR; arc=none smtp.client-ip=113.46.200.221 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="Ke0qftcR" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=yfy/kLuYSBUzok4FzwzCtdd1fXn+6YVgQIjQLkSKroQ=; b=Ke0qftcR4CIsMTXa4kh8sdaPvU5fo7TBaTBjvYEUJQxprcV9MtIMeDgPbPimuAalDTUdO2vgm /NRSgq7Uvx0l94NlDR809ZeHNvB4k43FgKX6jtLHBEB0gIxnX0sGXO9jily7/+JjkRKi5ybpPow 3AKCtua5TV5uaoTdoQrI4Fw= Received: from mail.maildlp.com (unknown [172.19.163.104]) by canpmsgout06.his.huawei.com (SkyGuard) with ESMTPS id 4hGb0L1blSzRhRG; Fri, 7 Aug 2026 15:10:58 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 6E2914058C; Fri, 7 Aug 2026 15:21:30 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 7 Aug 2026 15:21:29 +0800 Message-ID: <5a3389e5-53b8-4fc5-86b8-87fe689e1b60@huawei.com> Date: Fri, 7 Aug 2026 15:21:28 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] ARM: entry: Convert IRQ handling to generic IRQ entry To: Linus Walleij CC: "Paul E. McKenney" , Arnd Bergmann , Russell King , Oleg Nesterov , Thomas Gleixner , , References: <20260623-arm-generic-irq-entry-v7-1-v1-1-f25ca7079e3b@kernel.org> From: Jinjie Ruan In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To dggpemf500011.china.huawei.com (7.185.36.131) 在 2026/8/7 4:42, Linus Walleij 写道: > Hi Jinjie, > > sorry for slow return to this topic :/ > > On Sat, Jun 27, 2026 at 4:57 AM Jinjie Ruan wrote: > >> I have a small suggestion regarding the `interrupts_enabled` logic. If >> arm32 could also implement `regs_irqs_disabled(regs)` (similar to what >> arm64 and some other architectures already have), we might be able to >> unify this across subsystems. > > Yes, the patch implements this, hehe :) > >> Specifically, we could then replace the custom `interrupts_enabled` >> usage in both the arm64 architecture code and drivers like >> `drivers/irqchip/irq-gic-v3.c`. > > That should already be possible with this patch. > > I could also make a patch to replace all uses of interrupts_enabled() > with regs_irqs_disabled() as a follow-up to this patch (which introduces Yes, we can replace all interrupts_enabled() including irq-gic-v3.c and then remove the interrupts_enabled() in arch/arm64/include/asm/ptrace.h. https://lore.kernel.org/all/ZyDu9XHNmxMHBMSI@J2N7QTR9R3.cambridge.arm.com/ > regs_irqs_disabled()) if it gets accepted, I don't know if > that's a good idea though, maybe it makes the code harder > to read? > > Yours, > Linus Walleij