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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB52.mail.protection.outlook.com (10.167.241.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Fri, 13 Oct 2023 12:08:47 +0000 Received: from [192.168.137.2] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 13 Oct 2023 07:08:44 -0500 Message-ID: <5a3b6efe-5884-4727-a1e1-e9b8b0658523@amd.com> Date: Fri, 13 Oct 2023 14:08:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml Content-Language: en-US To: Krzysztof Kozlowski , "Praveen Teja Kundanala" , , , , , , CC: References: <20231013101450.573-1-praveen.teja.kundanala@amd.com> <20231013101450.573-3-praveen.teja.kundanala@amd.com> <02d3fa42-75a3-4f4f-ade6-204c8146d694@linaro.org> <91d61e1a-abb0-4b31-aa22-aff72d582ebe@amd.com> <013e44c6-45f5-44c1-94b3-536955fae78f@amd.com> From: Michal Simek Autocrypt: addr=michal.simek@amd.com; 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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|CH3PR12MB9314:EE_ X-MS-Office365-Filtering-Correlation-Id: ecde8736-7183-4204-9fea-08dbcbe5275f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W4Ukh3eZNpRaeaKsBeOA845ikjaHTBwFhNCEWsret2R+vY6UcCu6tAedWQHhYCXQm3hq9VLt4/Cdw5Ypry2PPbNJGb70HCetbA/F3cGOnBl/8w6XrkFT1+mRycPyKZQWagRAiuE80sKz8hm15Sasc8uTNGSgBvRYF7Mhtud+QuUwjGXeABIwMgJSb3lxqgucAvI1anPVnGJUJLlZDwE0sEf4aqlHVd+ytsZj2pvh6JCNW9yJfD7Jl6iyZyKKZI3cd32+BsrKNLETZ7jib/M8yDTgRToTqqyXAJtHLojio0hDIggkcJ8f+LxJ4wFwYr9/LTU8Oa24oAHwI3UaxAK27CjKcEhi8GOomJL63JeBbmdOkdDmAR0J48WkDXJvNbosBB24TfE1lqt6W4QXe+hjK5vH4uHLtj63FfVc0HiVjovb3ogcWwQrOeLYXTgtcm1jDIHvffovxnSVLKRdiWBRF+3OWQ9iMWPqPhVCHQ6mC1kD0POwPMbr94VMujdQha0aTnHN/9BksBj8gnhycBbldReosIbFWyuqEd9PB1dwiTYJOUy9iogLqrO2ozomskDURDVsx/jNIDGlB/ldzQVdqhmSsqJr5OKS4oVJGzhwcEZ7XlCVxonApD8GKHWbsUqaUoJkBG7pdMgZRyDs1wXANqkvcG26+fTICgmRxiTyWHj3y0tBcSX9zk4utpc4oLHc05iqQl4SHhcZZ14NrrQ8JRo7QTMfU5Me9VdKV88cFdW2y42yCDwUH3GgGGGFF7/cNgXAkvvlpUzmNXAekWURUJK8i8UDdR0Tr276dz+0VvadXC/UL6KcjSNLD3FoGtBG X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(346002)(376002)(396003)(39860400002)(230922051799003)(186009)(1800799009)(451199024)(64100799003)(82310400011)(36840700001)(46966006)(40470700004)(53546011)(316002)(16576012)(70586007)(2616005)(70206006)(110136005)(478600001)(31686004)(16526019)(26005)(8676002)(40480700001)(2906002)(8936002)(426003)(336012)(4326008)(36756003)(36860700001)(356005)(81166007)(83380400001)(41300700001)(5660300002)(44832011)(31696002)(86362001)(40460700003)(82740400003)(47076005)(36900700001)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 12:08:47.1115 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecde8736-7183-4204-9fea-08dbcbe5275f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9314 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/13/23 13:58, Krzysztof Kozlowski wrote: > On 13/10/2023 13:51, Michal Simek wrote: >> >> >> On 10/13/23 13:46, Krzysztof Kozlowski wrote: >>> On 13/10/2023 13:22, Michal Simek wrote: >>>>> >>>>>> + >>>>>> +required: >>>>>> + - compatible >>>>> >>>>> required: block goes after patternProperties: block >>>>> >>>>>> + >>>>>> +patternProperties: >>>>>> + "^soc_revision@0$": >>>>> >>>>> Why do you define individual memory cells? Is this part of a binding? >>>>> IOW, OS/Linux requires this? >>>> >>>> nvmem has in kernel interface where you can reference to nodes. nvmem_cell_get() >>>> calls. It means you should be able to describe internal layout that's why names >>>> are used. And address in name is there because of reg property is used to >>>> describe base offset and size. >>> >>> That's not really what I am asking. Why internal layout of memory must >>> be part of the bindings? >> >> It doesn't need to be but offsets are hardcoded inside the driver itself and >> they can't be different. > > Hm, where? I opened drivers/nvmem/zynqmp_nvmem.c and I do not see any > hard-coded offsets. Current driver supports only soc revision from offset 0. But if you look at 5/5 you need to define offsets where information is present. +#define SOC_VERSION_OFFSET 0x0 +#define EFUSE_START_OFFSET 0xC +#define EFUSE_END_OFFSET 0xFC +#define EFUSE_PUF_START_OFFSET 0x100 +#define EFUSE_PUF_MID_OFFSET 0x140 +#define EFUSE_PUF_END_OFFSET 0x17F > >> On different nvmem locations like MAC location in >> eeprom this can vary across boards but in this case location has to be only like >> this. >> I am fine if they don't need to be actually check but there is no any other way >> how they can be composed. And also others are not valid that's why not to >> describe only valid one. > > OK, that would be valid (if I find anywhere the offsets) and answers my > questions but I wish it was documented somewhere. Because now you are > making it a binding, so it cannot change (e.g. for different devices > with same hardware but different firmware or manufacturing process, for > future hardware sharing this binding). ZynqMP firmware with xlnx,zynqmp-nvmem-fw compatible string is using this map. If there is different firmware likely xlnx,zynqmp-nvmem-fw compatible string can't be used. > In any case the binding should have only items which are really fixed > and OS depends on them. Neither this nor next commit answers this. Actually 5/5 has this in commit message 0 - SOC version(read only) 0xC - 0xFC -ZynqMP specific purpose efuses 0x100 - 0x17F - Physical Unclonable Function(PUF) efuses repurposed as user efuses Thanks, Michal