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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b885b419288sm16929966b.20.2026.01.22.12.40.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jan 2026 12:40:54 -0800 (PST) Message-ID: <5a40a0ab-6c79-41b5-8741-c1bdcdeac617@oss.qualcomm.com> Date: Thu, 22 Jan 2026 21:40:52 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/4] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts To: Rob Herring , Pankaj Patil , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maulik Shah , Taniya Das , Manaf Meethalavalappu Pallikunhi , Jyothi Kumar Seerapu , Dmitry Baryshkov , Bjorn Andersson , Krzysztof Kozlowski , Sibi Sankar , Konrad Dybcio , Qiang Yu , Jishnu Prakash , Conor Dooley , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, Kamal Wadhwa , Abel Vesa References: <20260122-upstream_v3_glymur_introduction-v6-0-245f408ed82a@oss.qualcomm.com> <176910484203.3007057.6301998080301909826.robh@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <176910484203.3007057.6301998080301909826.robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ScZwLHuHd6d7J3n-Rg_w1EHaqLqZ6iZy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDE1OCBTYWx0ZWRfX5MfVITrvx16p GeOPSuc6GvRowsFM00D9b+VoXgoUbX6CL0YMqjVlcpa13eDdBGc1ALNgHv7c6Z99oFvEZAQpuw/ XjBAcuHqazYZC8Lkgyrbz2cujgf9LXW80UtrrSbA4MTesFGP6NkD0IgghKm+/WKnMIfWop1iWew 4XhhxI90WcF7g+g19WP6xsUHiQd7eZjFcpQhkQxVfBkUfl/vCdDOIIPdBIP1Glt5/zHPKaVNJHJ eFqJBbstyw0UyVWhwpoqg0TYbicHANa4Pl/xf4Pcn4EQDfl2AHY1dvWmx6aIxMqe3Sv4Plu1S5h B1EKYK5bfXUnhfF5ZAzE7zp7Sa5grOJsWaEJidvKf3bgyXV8ZV9yad39cSJFa9t8tYOf2DyRePp v3JGK7VsZ/W75509NTe+uvdrSXAi0BqOP8D9zHiKAUjAQFIi0Yr+vHvTUHlNFhy7FFHEyohwqgE LUryAlF1qiIAmSPnZUg== X-Authority-Analysis: v=2.4 cv=G+0R0tk5 c=1 sm=1 tr=0 ts=69728b58 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=qC_FGOx9AAAA:8 a=gEfo2CItAAAA:8 a=_jlGtV7tAAAA:8 a=YXyXsvO4i0MbaF_IcjgA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=fsdK_YakeE02zTmptMdW:22 a=sptkURWiP4Gy88Gu7hUp:22 a=nlm17XC03S6CtCLSeiRr:22 X-Proofpoint-GUID: ScZwLHuHd6d7J3n-Rg_w1EHaqLqZ6iZy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_04,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601220158 On 1/22/26 7:07 PM, Rob Herring wrote: > > On Thu, 22 Jan 2026 20:53:57 +0530, Pankaj Patil wrote: >> Introduce dt-bindings and initial device tree support for Glymur, >> Qualcomm's next-generation compute SoC and it's associated >> Compute Reference Device (CRD) platform. >> >> https://www.qualcomm.com/products/mobile/snapdragon/laptops-and-tablets/snapdragon-x2-elite >> https://www.qualcomm.com/news/releases/2025/09/new-snapdragon-x2-elite-extreme-and-snapdragon-x2-elite-are-the- >> >> The base support enables booting to shell with rootfs on NVMe, >> demonstrating functionality for PCIe and NVMe subsystems. >> DCVS is also enabled, allowing dynamic frequency scaling for the CPUs. >> TSENS (Thermal Sensors) enabled for monitoring SoC temperature and >> thermal management. The platform is capable of booting kernel at EL2 >> with kvm-unit tests performed on it for sanity. >> >> Added dtsi files for the PMIC's enabled PMH0101, PMK8850, PMCX0102, >> SMB2370, PMH0104, PMH0110 along with temp-alarm and GPIO nodeS. >> >> For CPU compatible naming, there is one discussion which is not specific >> to Glymur, Kaanapali and Glymur use the same Oryon cores. >> https://lore.kernel.org/all/20251119-oryon-binding-v1-1-f79a101b0391@oss.qualcomm.com/ >> We've kept the "qcom,oryon" compatible >> >> Features enabled in this patchset: >> 1. NVMe storage support >> 2. PCIe controller and PCIe PHY >> 3. RPMH Regulators >> 4. Clocks and reset controllers - GCC, TCSRCC, DISPCC, RPMHCC >> 5. Interrupt controller >> 6. TLMM (Top-Level Mode Multiplexer) >> 7. QUP Block >> 8. Reserved memory regions >> 9. PMIC support with regulators >> 10. CPU Power Domains >> 11. TSENS (Thermal Sensors) >> 12. DCVS: CPU DCVS with scmi perf protocol >> >> Dependencies: >> >> dt-bindings: >> 1. https://lore.kernel.org/all/20260121-glymur-pmic-mfd-v1-1-2aab4f21e79c@oss.qualcomm.com/ >> 2. https://lore.kernel.org/all/20251215-knp-pmic-leds-v3-2-5e583f68b0e5@oss.qualcomm.com/ >> 3. https://lore.kernel.org/all/20260121110828.2267061-1-pankaj.patil@oss.qualcomm.com/ >> 4. https://lore.kernel.org/all/20260111155234.5829-1-pankaj.patil@oss.qualcomm.com/ >> >> Linux-next based tree with Glymur patches is available at: >> https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/b4/v6_glymur_introduction >> >> Signed-off-by: Pankaj Patil >> --- >> Changes in v6: >> - Moved pmic thermal zones to their respective pmic dtsi files >> - Link to v5: https://lore.kernel.org/r/20260122-upstream_v3_glymur_introduction-v5-0-8ba76c354e9a@oss.qualcomm.com >> >> Changes in v5: >> - Added opp entries for pcie nodes >> - Dropped qup-memory interconnect from uart nodes >> - Update trip1 type to critical for pmic thermal zones >> - Alignment and newline fixes according to comments >> - Link to v4: https://lore.kernel.org/r/20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com >> >> Changes in v4: >> - Enabled PCIe SMMU for all 4 PCIe instances >> - Updated dispcc required opps level to "rpmhpd_opp_low_svs" >> - Updated watchdog compatible >> - Renamed gic-its to msi-controller >> - Updated GCC clocks property to 43 from 44 >> - Moved cpu-idle-states to domain-idle-states >> - Fixed alignment and zero padding issues according to review comments >> - Dropped glymur-pmics.dtsi >> - Moved pmic thermal zones from board dts to soc dtsi >> - Link to v3: https://lore.kernel.org/r/20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com >> >> Changes in v3: >> - Enabled system-cache-controller >> - Squashed all initial features to boot to shell with nvme as storage >> - Updated tsens nodes according to comments >> - Merged tcsr and tcsrcc node >> - Addressed review comments >> - Link to v1: https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com >> >> Changes in v2: >> - Series was sent erroneously >> - Link to v1: https://lore.kernel.org/r/20250925-v3_glymur_introduction-v1-0-5413a85117c6@oss.qualcomm.com >> >> Signed-off-by: Pankaj Patil >> >> --- >> Pankaj Patil (4): >> dt-bindings: arm: qcom: Document Glymur SoC and board >> arm64: defconfig: Enable Glymur configs for boot to shell >> arm64: dts: qcom: Introduce Glymur base dtsi >> arm64: dts: qcom: glymur: Enable Glymur CRD board support >> >> Documentation/devicetree/bindings/arm/qcom.yaml | 5 + >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/glymur-crd.dts | 601 +++ >> arch/arm64/boot/dts/qcom/glymur.dtsi | 5913 +++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 187 + >> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 68 + >> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 144 + >> arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 144 + >> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + >> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + >> arch/arm64/configs/defconfig | 5 + >> 11 files changed, 7183 insertions(+) >> --- >> base-commit: 46fe65a2c28ecf5df1a7475aba1f08ccf4c0ac1b >> change-id: 20251007-upstream_v3_glymur_introduction-5a105b54493d >> prerequisite-message-id: <20260121-glymur-pmic-mfd-v1-1-2aab4f21e79c@oss.qualcomm.com> >> prerequisite-patch-id: bd5a4703a5a7fc530418337680cf1e2ea1518f35 >> prerequisite-message-id: <20251215-knp-pmic-leds-v3-0-5e583f68b0e5@oss.qualcomm.com> >> prerequisite-patch-id: 6bbaff642cfd1f1386ff0ccd746739b68cdbeb45 >> prerequisite-patch-id: e30603778b23b7f7586b1c01a362e45af7bd0aa3 >> prerequisite-message-id: <20260121110828.2267061-1-pankaj.patil@oss.qualcomm.com> >> prerequisite-patch-id: 14469fd166b31b251b98bf25e783ab6f57ddd13a >> >> Best regards, >> -- >> Pankaj Patil >> >> >> > > > My bot found new DTB warnings on the .dts files added or changed in this > series. > > Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings > are fixed by another series. Ultimately, it is up to the platform > maintainer whether these warnings are acceptable or not. No need to reply > unless the platform maintainer has comments. > > If you already ran DT checks and didn't see these error(s), then > make sure dt-schema is up to date: > > pip3 install dtschema --upgrade > > > This patch series was applied (using b4) to base: > Deps: looking for dependencies matching 4 patch-ids > Deps: Applying prerequisite patch: [PATCH] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs present on Glymur > Deps: Applying prerequisite patch: [PATCH v3 1/2] dt-bindings: leds: leds-qcom-lpg: Add support for PMH0101 PWM > Deps: Applying prerequisite patch: [PATCH v3 2/2] dt-bindings: leds: qcom,spmi-flash-led: Add PMH0101 compatible > Deps: Applying prerequisite patch: [PATCH v2] dt-bindings: dma: qcom,gpi: Update max interrupt lines to 16 > Base: 46fe65a2c28ecf5df1a7475aba1f08ccf4c0ac1b (use --merge-base to override) > > If this is not the correct base, please add 'base-commit' tag > (or use b4 which does this automatically) > > > New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20260122-upstream_v3_glymur_introduction-v6-0-245f408ed82a@oss.qualcomm.com: > > arch/arm64/boot/dts/qcom/glymur-crd.dtb: pci@1bf0000 (qcom,glymur-pcie): compatible:0: 'qcom,pcie-x1e80100' was expected > from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml +Mani you sent a 'b4 ty' for this months ago, what happened? https://lore.kernel.org/linux-arm-msm/176189884156.5303.14323602106505981794.b4-ty@kernel.org/ The ipcc one should be handled by Rob now: https://lore.kernel.org/linux-arm-msm/20260116162057.GA1681736-robh@kernel.org/ And watchdog is perhaps in Guenter's queue https://lore.kernel.org/linux-arm-msm/de7f0b8a-a355-42c1-ac3c-d0b5de754711@roeck-us.net/ Konrad