From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: "Mark Brown" <broonie@kernel.org>, "Vignesh R" <vigneshr@ti.com>,
"Tudor Ambarus" <tudor.ambarus@microchip.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-spi <linux-spi@vger.kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"Miquèl Raynal" <miquel.raynal@bootlin.com>,
"Simon Goldschmidt" <simon.k.r.goldschmidt@gmail.com>,
"Dinh Nguyen" <dinguyen@kernel.org>,
"Richard Weinberger" <richard@nod.at>,
cheol.yong.kim@intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
Date: Fri, 6 Nov 2020 12:33:06 +0800 [thread overview]
Message-ID: <5a4f6085-0408-d5e5-5f40-efc7814cbe42@linux.intel.com> (raw)
In-Reply-To: <CACRpkdZnAfogewQt83wDMmkhb4kZD=qdbq26nHcam3401WGiOA@mail.gmail.com>
Hi Linus,
Thank you for the review comments...
On 5/11/2020 3:11 pm, Linus Walleij wrote:
> On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX
> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>
>> + ddata = of_device_get_match_data(dev);
>> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
>> + if (of_property_read_u32(np, "num-chipselect",
>
> The standard SPI bindings in spi-controller.yaml already has a binding
> for this "num-cs" so please use that. It is also what your device tree
> binding is referencing,
yes, you are point is valid, I will use that.
so if you were using "num-chipselect" the
> YAML check should give a warning?
In the example, I just converted from existing txt -to- yaml that's
why I didnt face any problem.
Regards
Vadivel
>
> Yours,
> Linus Walleij
>
next prev parent reply other threads:[~2020-11-06 4:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-30 5:31 [PATCH v6 0/6] spi: cadence-quadspi: Add QSPI controller " Ramuthevar,Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
2020-11-03 16:09 ` Pratyush Yadav
2020-11-04 9:18 ` Ramuthevar, Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
2020-11-05 7:11 ` Linus Walleij
2020-11-06 4:33 ` Ramuthevar, Vadivel MuruganX [this message]
2020-10-30 5:31 ` [PATCH v6 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-30 15:18 ` Rob Herring
2020-11-02 5:59 ` Ramuthevar, Vadivel MuruganX
2020-11-04 22:02 ` Rob Herring
2020-11-09 1:40 ` Ramuthevar, Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-11-04 22:03 ` Rob Herring
2020-11-09 1:49 ` Ramuthevar, Vadivel MuruganX
2020-11-09 15:15 ` Rob Herring
2020-11-10 5:21 ` Ramuthevar, Vadivel MuruganX
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