From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 812A2C46467 for ; Sat, 14 Jan 2023 08:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229573AbjANItq (ORCPT ); Sat, 14 Jan 2023 03:49:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229468AbjANIto (ORCPT ); Sat, 14 Jan 2023 03:49:44 -0500 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C32659E4 for ; Sat, 14 Jan 2023 00:49:42 -0800 (PST) Received: from dggpeml500002.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4NvBkZ55lSz16Mm9; Sat, 14 Jan 2023 16:47:50 +0800 (CST) Received: from [10.67.103.44] (10.67.103.44) by dggpeml500002.china.huawei.com (7.185.36.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 14 Jan 2023 16:49:29 +0800 Subject: Re: [PATCH] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR To: Anshuman Khandual , , , , References: <20230110125101.10533-1-hejunhao3@huawei.com> CC: , , , , , From: hejunhao Message-ID: <5a834f93-f32b-c926-2bec-e00e35aa864f@huawei.com> Date: Sat, 14 Jan 2023 16:49:29 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.103.44] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500002.china.huawei.com (7.185.36.158) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023/1/12 11:48, Anshuman Khandual wrote: > > On 1/10/23 18:21, Junhao He wrote: >> The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the > s/register is/registers are/ Ok, will fix it. Thanks. >> TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. > s/register/registers/ Ok, will fix it. Thanks. >> Signed-off-by: Junhao He > Reviewed-by: Anshuman Khandual > >> --- >> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ >> 1 file changed, 12 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 80fefaba58ee..c7a65d1524fc 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) >> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); >> - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); >> for (i = 0; i < drvdata->nr_cntr; i++) { >> etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); >> @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); >> >> - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + } >> state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); >> >> for (i = 0; i < drvdata->nr_cntr; i++) { >> @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); >> >> - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); >> >> for (i = 0; i < drvdata->nr_cntr; i++) { > . >