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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7e2a0a008e2sm1225681b3a.28.2025.12.03.23.45.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Dec 2025 23:45:16 -0800 (PST) Message-ID: <5a982965-4964-4f50-87b6-e3b8a1182876@oss.qualcomm.com> Date: Thu, 4 Dec 2025 15:44:50 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Luo Jie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com References: <20251128-qcom_ipq5332_cmnpll-v1-0-55127ba85613@oss.qualcomm.com> <20251128-qcom_ipq5332_cmnpll-v1-1-55127ba85613@oss.qualcomm.com> <2d83f0d3-4798-4183-9e3d-9972db706cdb@oss.qualcomm.com> <1d9b953b-5af0-4a81-9182-f1cd47e772f1@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: <1d9b953b-5af0-4a81-9182-f1cd47e772f1@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=GMMF0+NK c=1 sm=1 tr=0 ts=69313c0d cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=MGsDpFW7tt7mzu13zmcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: Oqs9FmPafCdc-FmZsafHLtmSX9LAgfPe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDA2MSBTYWx0ZWRfX7P+DLte7nbNe MObY69Y1VEIQescikNovxsLVGTxbzeEzDXF56kBFM4iBmVw4rDcmMAMsBLTvWATffvf4V3OmD2w V2vUb27m06SpWk6FwIhcO1VBqWhKileg5UBQTJqlzHW5ZJgzdQQs2wfv3NKBNbogzeob2ZPmUEJ pd95o2h/7EPD4/i2BO7Dbe6L5b7MvL8Z81daKnknZnw6ayE8cOGkUOL6dnVzyCX2wEJGS3HcEgA 7vPp8ruXcCeKOMK+pYSjDlkJo3iaygW6zsyDblShSXKGvjQaQmXSdpR1w4yQlj+kzHaW/FTulFU D5D/Lcz0i7WPSP/eHMvuGpwVfDgbyhQM0VA2S/bqXdYV4VcBiVA/BPq6Jvhz2BOMGAtg/j2gmSz CE79ZnSfqTduJ0rejQjsnQqOaMRNfA== X-Proofpoint-GUID: Oqs9FmPafCdc-FmZsafHLtmSX9LAgfPe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_02,2025-12-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040061 On 12/1/2025 9:42 PM, Konrad Dybcio wrote: > On 11/28/25 3:29 PM, Jie Luo wrote: >> >> >> On 11/28/2025 7:38 PM, Konrad Dybcio wrote: >>> On 11/28/25 9:40 AM, Luo Jie wrote: >>>> The clk_cmn_pll_recalc_rate() function must account for the reference clock >>>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms >>>> with a reference divider other than 1 calculate incorrect CMN PLL rates. >>>> For example, on IPQ5332 where the reference divider is 2, the computed rate >>>> becomes twice the actual output. >>>> >>>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before >>>> applying the 2 * FACTOR scaling. This yields the correct rate calculation: >>>> rate = (parent_rate / ref_div) * 2 * factor. >>>> >>>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574, >>>> IPQ5424, IPQ5018) that use ref_div = 1. >>> >>> I'm not sure how to interpret this. Is the value fixed on these platforms >>> you mentioned, and always shows up as 0? >>> >>> Konrad >> >> On these platforms the hardware ref_div register comes up with a value >> of 1 by default. It is, however, still a programmable field and not >> strictly fixed to 1. >> >> The ref_div == 0 check in this patch is only meant as a safety net to >> avoid a divide‑by‑zero in the rate calculation. > > I think some sort of a warning/bugsplat would be good to have here, > however I see that clk-rcg2.c : clk_gfx3d_determine_rate() apparently > also silently fixes up a div0.. > > Konrad I agree it would be better to at least flag this as an invalid configuration. I can update the code to emit a warning (e.g. WARN_ON (!ref_div) while still clamping ref_div to a sane value to avoid crashing in production. That way we preserve the safety net but also get some visibility if this ever happens.