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> ``` > should be: > ``` > if (evsel->precise_max) > attr->precise_ip = evsel->pmu->max_precise; > ``` This segfaults as evsel->pmu is NULL. But I get your point. If we go with this change, I'll need to switch to cycles:p as default event on AMD. Otherwise perf will use non-precise event as default event on AMD. > Presumably this is misreporting as some non-zero value on the buggy > systems - if it doesn't we can declare victory here. If not we can > modify max_precise's calculation on perf's struct pmu for cpu for AMD > so that we just hardwire it to zero in arch code. max_precise for AMD core pmu is 0, which is correct as AMD core pmu does not support precise mode. However, cycles:p, r76:p and rC1:p are special cases and allowed via core pmu. Thanks, Ravi