From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81F2B188CC9 for ; Sun, 22 Dec 2024 15:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734881832; cv=none; b=q/4pmOZFfOKeXkoewsVk+xhhp4OkkJYuudPqgAXqcK28ao7uf/GFsG7GX6G72HR3GmVg3NDkM6DrupioiZZdLu9I7g6tTZR14pK/NBjt8rFEFudK443ze27tvPv+mAgQ/HH1E/cy9KMC/YiU+X8MZInFL+mcEL26Rb4dW/ClUYU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734881832; c=relaxed/simple; bh=o2I/N3Z4vkl24Dh0ssHRyKOlPOzX1XiNpankoYQY2Sc=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=f2FiNwQ51wXEaGPsC70pKxcvx2rF4LfvZMWJWsAdp2oJmV7Rg/2WsjGKNtCmERPDvk2dgLBcnd06ZhLzVmSBMrQn++XxskYhcbQm60RYPai6idjXhX8/Dxb6EeJRR+Xgq+iDEXJvd7F8usd9Po7vpgWH+dC0HFaMlizuW5sDCZE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPO0r-000000001fz-2iXv; Sun, 22 Dec 2024 10:37:01 -0500 Message-ID: <5ae11e5ac6b278de9ad2ad2badbd5f010543d934.camel@surriel.com> Subject: Re: [PATCH 09/10] x86/mm: enable AMD translation cache extensions From: Rik van Riel To: Peter Zijlstra Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org Date: Sun, 22 Dec 2024 10:37:01 -0500 In-Reply-To: <20241222113811.GY11133@noisy.programming.kicks-ass.net> References: <20241222040717.3096835-1-riel@surriel.com> <20241222040717.3096835-10-riel@surriel.com> <20241222113811.GY11133@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Sun, 2024-12-22 at 12:38 +0100, Peter Zijlstra wrote: > On Sat, Dec 21, 2024 at 11:06:41PM -0500, Rik van Riel wrote: > > With AMD TCE (translation cache extensions) only the intermediate > > mappings >=20 > Only the leave mapings, as written this all don't make sense, Check out page 513 of the AMD manual: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/progra= mmer-references/40332.pdf "Translation Cache Extension (TCE) Bit. Bit 15, read/write.=C2=A0 Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all=C2=A0 upper-level table entries that are cached in the TLB, whether or=C2=A0 not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those=C2=A0 upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. This may provide a performance benefit. Page table management software must be written in a way that takes=C2=A0 this behavior into account. Software that was written for a=C2=A0 processor that does not cache upper-level table entries may result=C2=A0 in stale entries being incorrectly used for translations when TCE=C2=A0 is enabled. Software that is compatible with TCE mode will operate in either mode. For software using INVLPGB to broadcast TLB invalidations, the invalidations are controlled by the EFER.TCE value on the processor executing the INVLPGB instruction. Before setting TCE, system software should verify that this feature is supported by examining the feature flag CPUID Fn8000_0001_ECX[TCE]. See Section 3.3 =E2=80=9CProcessor Feature Identification,=E2=80=9D on page 71 for information on using the CPUID instruction" This suggests that: 1) TCE does control the "don't make sense" behavior :) 2) Wait, does EFER.TCE need to be set on every CPU in the system? Could a system run with TCE set on some CPUs, and cleared on another?! It would be nice if somebody from AMD could chime in on the latter, and ensure that this patch actually does the right thing :) I'll incorporate all the other feedback from you and Borislav into the next version of the patch series! Thank you for the feedback. --=20 All Rights Reversed.