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[83.9.30.30]) by smtp.gmail.com with ESMTPSA id u24-20020ac25198000000b004eeec1261ecsm1457547lfi.31.2023.06.23.06.58.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Jun 2023 06:58:10 -0700 (PDT) Message-ID: <5b68b9ba-157b-067c-3926-9c5ecfecc311@linaro.org> Date: Fri, 23 Jun 2023 15:58:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Content-Language: en-US To: neil.armstrong@linaro.org, Andy Gross , Bjorn Andersson , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton References: <20230619-topic-sm8550-upstream-interconnect-mask-vote-v2-0-709474b151cc@linaro.org> From: Konrad Dybcio Subject: Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote In-Reply-To: <20230619-topic-sm8550-upstream-interconnect-mask-vote-v2-0-709474b151cc@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.06.2023 14:50, neil.armstrong@linaro.org wrote: > On the SM8550 SoC, some nodes requires a specific bit mark > instead of a bandwidth when voting. > > Add an enable_mask variable to be used instead of bandwidth. > > Signed-off-by: Neil Armstrong > --- After reviewing this patchset and taking a peek at older downstream, it looks like ACV should be using 0x8 bmask on *all RPMh SoCs*. It's worth noting however, that 8350's downstream (the first msm kernel using the icc framework) did not incorporate that change. Not sure if intentionally or not. Probably not. Might be worth to poke Qcom to backport it in such case. If 8350 is still supported. Probably not. Check out these snippets: https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L556-567 https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L475-495 Notice how acv is never updated beyond effectively setting =0 or =bmask, perhaps Qualcomm never implemented something else.. Since this series is fine as-is, I'd be happy to see an incremental one. Reported-by would be cool as well :D Konrad > Changes in v2: > - Took downstream patch for patch 1 > - Added konrad's reviewed tag > - Added changes for sm8450 and sa8775p > - Link to v1: https://lore.kernel.org/r/20230619-topic-sm8550-upstream-interconnect-mask-vote-v1-0-66663c0aa592@linaro.org > > --- > Mike Tipton (1): > interconnect: qcom: Add support for mask-based BCMs > > Neil Armstrong (3): > interconnect: qcom: sm8450: add enable_mask for bcm nodes > interconnect: qcom: sm8550: add enable_mask for bcm nodes > interconnect: qcom: sa8775p: add enable_mask for bcm nodes > > drivers/interconnect/qcom/bcm-voter.c | 5 +++++ > drivers/interconnect/qcom/icc-rpmh.h | 2 ++ > drivers/interconnect/qcom/sa8775p.c | 1 + > drivers/interconnect/qcom/sm8450.c | 9 +++++++++ > drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++ > 5 files changed, 34 insertions(+) > --- > base-commit: 47045630bc409ce6606d97b790895210dd1d517d > change-id: 20230619-topic-sm8550-upstream-interconnect-mask-vote-96aa20355158 > > Best regards,