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Thu, 05 Nov 2026 01:47:21 -0800 (PST) Received: from [192.168.0.167] ([51.37.126.136]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48fed45d71dsm8886594f8f.36.2026.11.05.01.47.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Nov 2026 01:47:20 -0800 (PST) Message-ID: <5ba03b8e-1d51-4e66-a802-37e63814f5d5@linaro.org> Date: Thu, 5 Nov 2026 09:47:19 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS To: Vladimir Zapolskiy , mail@andrewgigena.dev, Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org References: <20261104-sm8150-v7-4-rc1-camss-v1-0-7a9534a9a22f@andrewgigena.dev> <20261104-sm8150-v7-4-rc1-camss-v1-2-7a9534a9a22f@andrewgigena.dev> <904675e8-701d-4fd6-b418-6c0dcc9288b9@linaro.org> From: Bryan O'Donoghue Content-Language: en-GB In-Reply-To: <904675e8-701d-4fd6-b418-6c0dcc9288b9@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 04/11/2026 23:16, Vladimir Zapolskiy wrote: >> +maintainers: >> +  - Andrew Gigena >> + >> +description: | >> +  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. >> + >> +properties: >> +  compatible: >> +    const: qcom,sm8150-camss >> + >> +  clocks: >> +    minItems: 42 >> +    maxItems: 42 >> + >> +  clock-names: >> +    items: >> +      - const: camnoc_axi >> +      - const: camnoc_axi_src >> +      - const: cpas_ahb >> +      - const: cphy_rx_src >> +      - const: csiphy0 >> +      - const: csiphy0_timer >> +      - const: csiphy0_timer_src >> +      - const: csiphy1 >> +      - const: csiphy1_timer >> +      - const: csiphy1_timer_src >> +      - const: csiphy2 >> +      - const: csiphy2_timer >> +      - const: csiphy2_timer_src >> +      - const: csiphy3 >> +      - const: csiphy3_timer >> +      - const: csiphy3_timer_src > > Please switch to the new model of describing and exploiting > the stand-alone CSI2 PHY devices. > > Any CAMSS drivers based on the legacy description of CSIPHYs > should not be accepted into the upstream. I mean we are just adding a new define for a SoC here - not a new init sequence. We could move all of sc8280xp, sm8150 and sm8250 to a new driver topology but, I don't think that's a reasonable ask for a small change like this from a new contributor. Certainly would welcome the transition given above as a defined and neat series but, I don't think there's a need for that to include this SoC in 100% existing infrastructure. --- bod