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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b0423ed35e4sm1961096966b.25.2025.09.08.08.39.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 08:39:08 -0700 (PDT) Message-ID: <5bbe77f0-185f-4905-8097-8769f0d5f518@oss.qualcomm.com> Date: Mon, 8 Sep 2025 17:39:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes To: rob.clark@oss.qualcomm.com, Akhil P Oommen Cc: Dmitry Baryshkov , Sean Paul , Konrad Dybcio , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Connor Abbott , Srinivas Kandagatla , Dmitry Baryshkov , Gaurav Kohli , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Puranam V G Tejaswi References: <20250822-a663-gpu-support-v4-0-97d26bb2144e@oss.qualcomm.com> <20250822-a663-gpu-support-v4-3-97d26bb2144e@oss.qualcomm.com> <14b5db9f-8b31-4baa-a03d-12112425fbbe@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMiBTYWx0ZWRfX3dSr340dQeuy 1Xnu3WaPwzsvzo/KHdBWHQBejYjK/OwkGsokHBbmt3ky/21macZITAZpK/7XbuW12jL3Oo8fWCu sM+JsYZ9HUZj2qDBxo3XHowxveU8hdvdSKlG0aMXUudGzvBXGeqI1q2aaomCEYENPk4Uprhi09+ 67hQfrxQe5KCKfVR9BO97/sfdpmNsT3u9lYoLavGiCcn7qmn7KD5AwUDmrUZ24ghzzrKvdjL+c4 vRUAgA/2HDW21AZpKGR8j9kj44x8Lz6GiWOXSsHL7Zb6OkFZ732WTgOmKwA867O4HrLloZt+0pV lds/3YtDM8zdnNVLrTNefT7fsWn2UUaUA9AoQZQ2xTHCSKO2iG/HmvKBOB9M8xyW4oWg0OjQDBX nkvTuCRa X-Proofpoint-ORIG-GUID: JeMu148q03rwadKMBAvS3DGZjzEe2XEG X-Authority-Analysis: v=2.4 cv=PpOTbxM3 c=1 sm=1 tr=0 ts=68bef89e cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=am1a1fgwjgo6KoPeU6gA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: JeMu148q03rwadKMBAvS3DGZjzEe2XEG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_05,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060022 On 9/7/25 1:02 AM, Rob Clark wrote: > On Sat, Sep 6, 2025 at 1:56 PM Akhil P Oommen wrote: >> >> On 9/3/2025 8:44 PM, Konrad Dybcio wrote: >>> On 9/3/25 4:00 PM, Dmitry Baryshkov wrote: >>>> On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio wrote: >>>>> On 9/3/25 2:39 PM, Dmitry Baryshkov wrote: >>>>>> On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote: >>>>>>> On 8/21/25 8:55 PM, Akhil P Oommen wrote: >>>>>>>> From: Puranam V G Tejaswi >>>>>>>> >>>>>>>> Add gpu and gmu nodes for sa8775p chipset. As of now all >>>>>>>> SKUs have the same GPU fmax, so there is no requirement of >>>>>>>> speed bin support. >>>>>>>> >>>>>>>> Signed-off-by: Puranam V G Tejaswi >>>>>>>> Signed-off-by: Akhil P Oommen >>>>>>>> Reviewed-by: Dmitry Baryshkov >>>>>>>> --- >>>>>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 116 +++++++++++++++++++++++++++++++++++ >>>>>>>> 1 file changed, 116 insertions(+) >>>>>>>> >>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>>>> index 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c 100644 >>>>>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>>>> @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 { >>>>>>>> #mbox-cells = <2>; >>>>>>>> }; >>>>>>>> >>>>>>>> + qfprom: efuse@784000 { >>>>>>>> + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; >>>>>>>> + reg = <0x0 0x00784000 0x0 0x2410>; >>>>>>> >>>>>>> len = 0x3000 >>>>>>> >>>>>>> [...] >>>>>>> >>>>>>>> + gmu: gmu@3d6a000 { >>>>>>>> + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; >>>>>>>> + reg = <0x0 0x03d6a000 0x0 0x34000>, >>>>>>> >>>>>>> This bleeds into GPU_CC, len should be 0x26000 >>>>>> >>>>>> gpucc is in the middle of GMU, see other platforms. >>>>> >>>>> This is not the case here >>>> >>>> Why? I think GPU CC is a part of the GMU by design: GMU accesses GPU CC >>>> registers directly from the firmware. >>> >>> Correct, however this is only a similarly sounding argument - the DT >>> describes the hardware from the main Arm cluster POV. The GMU Cortex-M >>> core has its own address map etc. > > but the firmware is part of how the hardware appears to the main arm cluster > >> We have been keeping GPUCC region in the GMU's reg range in all chipsets >> for the purpose of coredump. >> >> Can we leave this as is until we have a mechanism to dump these into gpu >> coredump (via gpucc driver??)? I recall you proposed something similar >> sometime back. > > IMO we should keep this in the GMU range.. if in the future we have > some other mechanism to dump gpucc state, then for future platforms we > can start using that (ie. new dt but old kernel should be a thing we > at least pretend to try to keep working), but for current/past > platforms we should stick with keeping this in the GMU's range Eh, right, sorry, we discussed this with I think x1e, let's keep it as-is until more infra is in place Konrad