From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63374136E3B for ; Thu, 23 Jan 2025 12:42:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737636185; cv=none; b=GlRrYmY6A7LHr0JoYNhkqw7twZYQw82eu4cOT1fLvEAi/lEpAnx/qPpTalRhR0Wn9N4RlEO5JqKho5edhg4mz3sAu2zlY9TECw5rkhUnEJvGyzdlLPzRx4rlDhpF/HICzEwEe+ImCr+eYwnHPja2hCmXOqdq3AOdmpt9j64MxX8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737636185; c=relaxed/simple; bh=e/Jqxk85JjejtfpBPsnKlYVmotJws6uqQaxJ7bF48Uw=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=G0SbjZgevq8VXieF5JDh2T1umN0WULtPGDMeOp5+xLVmN2f4BWQrhKwQkHSDeUHZCfjZsjK6BvB/ZUpoF8IhPjjv9LXeP5d/lyTb5v539MhUvLBAHHW/IDFE1RxJcxzw0B8bd20TbMGKMTtEFzOTNw9otsFUfXv36VaAFhjsFTA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tawXe-000000003KH-16og; Thu, 23 Jan 2025 07:42:38 -0500 Message-ID: <5bdc9986fb755d84e31d4550a7d2a8ec9e7b0fa3.camel@surriel.com> Subject: Re: [PATCH v6 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes From: Rik van Riel To: Peter Zijlstra Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Mark Rutland , Will Deacon Date: Thu, 23 Jan 2025 07:42:38 -0500 In-Reply-To: <20250123090720.GI3808@noisy.programming.kicks-ass.net> References: <20250120024104.1924753-1-riel@surriel.com> <20250120024104.1924753-10-riel@surriel.com> <20250122083835.GE7145@noisy.programming.kicks-ass.net> <5820b18ef0ba48c33a62553fcc444c47f963b907.camel@surriel.com> <20250123090720.GI3808@noisy.programming.kicks-ass.net> Autocrypt: addr=riel@surriel.com; prefer-encrypt=mutual; keydata=mQENBFIt3aUBCADCK0LicyCYyMa0E1lodCDUBf6G+6C5UXKG1jEYwQu49cc/gUBTTk33A eo2hjn4JinVaPF3zfZprnKMEGGv4dHvEOCPWiNhlz5RtqH3SKJllq2dpeMS9RqbMvDA36rlJIIo47 Z/nl6IA8MDhSqyqdnTY8z7LnQHqq16jAqwo7Ll9qALXz4yG1ZdSCmo80VPetBZZPw7WMjo+1hByv/ lvdFnLfiQ52tayuuC1r9x2qZ/SYWd2M4p/f5CLmvG9UcnkbYFsKWz8bwOBWKg1PQcaYHLx06sHGdY dIDaeVvkIfMFwAprSo5EFU+aes2VB2ZjugOTbkkW2aPSWTRsBhPHhV6dABEBAAG0HlJpayB2YW4gU mllbCA8cmllbEByZWRoYXQuY29tPokBHwQwAQIACQUCW5LcVgIdIAAKCRDOed6ShMTeg05SB/986o gEgdq4byrtaBQKFg5LWfd8e+h+QzLOg/T8mSS3dJzFXe5JBOfvYg7Bj47xXi9I5sM+I9Lu9+1XVb/ r2rGJrU1DwA09TnmyFtK76bgMF0sBEh1ECILYNQTEIemzNFwOWLZZlEhZFRJsZyX+mtEp/WQIygHV WjwuP69VJw+fPQvLOGn4j8W9QXuvhha7u1QJ7mYx4dLGHrZlHdwDsqpvWsW+3rsIqs1BBe5/Itz9o 6y9gLNtQzwmSDioV8KhF85VmYInslhv5tUtMEppfdTLyX4SUKh8ftNIVmH9mXyRCZclSoa6IMd635 Jq1Pj2/Lp64tOzSvN5Y9zaiCc5FucXtB9SaWsgdmFuIFJpZWwgPHJpZWxAc3VycmllbC5jb20+iQE +BBMBAgAoBQJSLd2lAhsjBQkSzAMABgsJCAcDAgYVCAIJCgsEFgIDAQIeAQIXgAAKCRDOed6ShMTe g4PpB/0ZivKYFt0LaB22ssWUrBoeNWCP1NY/lkq2QbPhR3agLB7ZXI97PF2z/5QD9Fuy/FD/jddPx KRTvFCtHcEzTOcFjBmf52uqgt3U40H9GM++0IM0yHusd9EzlaWsbp09vsAV2DwdqS69x9RPbvE/Ne fO5subhocH76okcF/aQiQ+oj2j6LJZGBJBVigOHg+4zyzdDgKM+jp0bvDI51KQ4XfxV593OhvkS3z 3FPx0CE7l62WhWrieHyBblqvkTYgJ6dq4bsYpqxxGJOkQ47WpEUx6onH+rImWmPJbSYGhwBzTo0Mm G1Nb1qGPG+mTrSmJjDRxrwf1zjmYqQreWVSFEt26tBpSaWsgdmFuIFJpZWwgPHJpZWxAZmIuY29tP okBPgQTAQIAKAUCW5LbiAIbIwUJEswDAAYLCQgHAwIGFQgCCQoLBBYCAwECHgECF4AACgkQznneko TE3oOUEQgAsrGxjTC1bGtZyuvyQPcXclap11Ogib6rQywGYu6/Mnkbd6hbyY3wpdyQii/cas2S44N cQj8HkGv91JLVE24/Wt0gITPCH3rLVJJDGQxprHTVDs1t1RAbsbp0XTksZPCNWDGYIBo2aHDwErhI omYQ0Xluo1WBtH/UmHgirHvclsou1Ks9jyTxiPyUKRfae7GNOFiX99+ZlB27P3t8CjtSO831Ij0Ip QrfooZ21YVlUKw0Wy6Ll8EyefyrEYSh8KTm8dQj4O7xxvdg865TLeLpho5PwDRF+/mR3qi8CdGbkE c4pYZQO8UDXUN4S+pe0aTeTqlYw8rRHWF9TnvtpcNzZw== Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Thu, 2025-01-23 at 10:07 +0100, Peter Zijlstra wrote: > On Wed, Jan 22, 2025 at 08:13:03PM -0500, Rik van Riel wrote: > > On Wed, 2025-01-22 at 09:38 +0100, Peter Zijlstra wrote: > > >=20 > > > Looking at this more... I'm left wondering, did 'we' look at any > > > other > > > architecture code at all?=20 > > >=20 > > > For example, look at arch/arm64/mm/context.c and see how their > > > reset > > > works. Notably, they are not at all limited to reclaiming free'd > > > ASIDs, > > > but will very aggressively take back all ASIDs except for the > > > current > > > running ones. > > >=20 > > I did look at the ARM64 code, and while their reset > > is much nicer, it looks like that comes at a cost on > > each process at context switch time. > >=20 > > In new_context(), there is a call to check_update_reserved_asid(), > > which will iterate over all CPUs to check whether this > > process's ASID is part of the reserved list that got > > carried over during the rollover. > >=20 > > I don't know if that would scale well enough to work > > on systems with thousands of CPUs. >=20 > So assuming something like 1k CPUs and !PTI, we only have like 4 > PCIDs > per CPU on average, and rollover could be frequent. >=20 > While an ARM64 with 1k CPUs and !PTI would have an average of 64 > ASIDs > per CPU, and rollover would be far less frequent. Not necessarily. On ARM64, every short lived task will get a global ASID, while on x86_64 only longer lived processes that are simultaneously active on multiple CPUs get a global ASID. The situation could be fairly bad for both, which is why I would like to solve the O(n^2) issues with the rollover code before adding that in to our x86_64 side :) I fully agree we should probably move in that direction, but I would like to make the worst case in the rollover-reuse cheaper. >=20 > That is to say, their larger ASID space (16 bits, vs our 12) > definitely > helps. But at some point yeah, this will become a problem. >=20 > Notably, I think think a 2 socket Epyc Turin with 192C is one of the > larger off-the-shelf systems atm, that gets you 768 CPUs and that is > already uncomfortably tight with our PCID space. >=20 >=20 >=20 --=20 All Rights Reversed.