From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 968DA283FCE for ; Sun, 2 Aug 2026 16:17:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687431; cv=none; b=VJAH/7ya2uW1Rb3p8V2PAbo5Ac208EhdqHFoBZ0PWhSlleOT7Sun8goVqlS5SKk1v1vfEQZ/bFhFLC6jX0B61cvc2mb7JWBDq3pG9yO9crgJRJZjJlaH65nTNVZ2ULgGSGfLSOmsMVbqXpn5/qZpz2tX8P5J2csH1eYEs5+WRbg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687431; c=relaxed/simple; bh=Zg/L4qgd1Rh5Ja4SBJwAWvJpl9dI5jMS/OzZQ/ScmZE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i9sc9ani3eR5co/xPrxpTFINlwVPjBXSDaWqaHVo1q9PM4UU2zUOlSTWNJPIE6q+O4OmPiFYvzUPGX9TVx2Pfvpi4z6LdgwHA1zO3vsFgOX1gKkJ27oFyWH/Gw4Vkdxo2XEG9iikjssTfPhasO3/FxuJ9lx86YAHlsDQ/pQY0sU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AvcdNfhz; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AvcdNfhz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687429; x=1817223429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zg/L4qgd1Rh5Ja4SBJwAWvJpl9dI5jMS/OzZQ/ScmZE=; b=AvcdNfhznAbmZMc2nA75/l0mRvOCoaiF1k32FcRcHqVSkzyIhfTQafx6 A/dnmlY9h2vqBy7r7WKul6jQkUKRQAylCmQwUWWKjau/JkUckI4oCPj8q nTFCwMFPMZ+XVYTEPmRs0XAfNMFZLTJID16UN9HYkKZniTJ5gPAIoh3lY 6Q5D8iCC7hVaNBPElTAQRYadFCCbvL3h7NLcbzKMhhq5l3VaT9CwQAeEV SL9aIll8xyqdmpiFWbjp4U8nhBuAzlp++qlVJ5yfJj0qmRD6EeHqRFO+E NniU4MI/CNkPRtUz1/HdfPTwh4k5uGz9Lta9c4QYaLHFzscQgWNwuvoC7 Q==; X-CSE-ConnectionGUID: pj15FFPtQ/eKCAjfQ6KqXg== X-CSE-MsgGUID: KO6ESy8CTJa4jHiS317ElA== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="86101079" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="86101079" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:17:05 -0700 X-CSE-ConnectionGUID: OQtR+gEpQkWDN4EhuSmcew== X-CSE-MsgGUID: 1hctSxkNTb6L4ouBHbngbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="285634144" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by fmviesa001.fm.intel.com with ESMTP; 02 Aug 2026 09:17:01 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 23/31] x86/resctrl: Add region aware MBA controllers Date: Mon, 3 Aug 2026 00:07:20 +0800 Message-Id: <5be04c91594bfdbd29951cc86b786228fc71fee8.1785680802.git.yu.c.chen@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add region aware MBA controllers for ERDT platforms that have the MARC (Memory-bandwidth Allocation Registers for CPU Agents) ACPI subtable. For each memory region reported by MRRM, create OPT, MIN, and MAX controllers (as indicated by MARC flags) using resctrl_ctrl_name_region(). The controller properties (bandwidth range, granularity, unit) are derived from the MARC subtable fields. The hw_update callback is a stub for now; the actual MMIO write implementation will follow in a subsequent patch. Signed-off-by: Chen Yu --- arch/x86/kernel/cpu/resctrl/core.c | 3 ++ arch/x86/kernel/cpu/resctrl/erdt.c | 67 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 5 ++ 3 files changed, 75 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 0bde098db41e..b2c53eab7d8f 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1063,6 +1063,9 @@ static __init bool get_rdt_alloc_resources(void) if (get_mem_config()) ret = true; + if (erdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl)) + ret = true; + if (get_slow_mem_config()) ret = true; diff --git a/arch/x86/kernel/cpu/resctrl/erdt.c b/arch/x86/kernel/cpu/resctrl/erdt.c index c44e1d00b89f..b61f75b63f37 100644 --- a/arch/x86/kernel/cpu/resctrl/erdt.c +++ b/arch/x86/kernel/cpu/resctrl/erdt.c @@ -21,6 +21,7 @@ static LIST_HEAD(domain_info_list); /* True when the ERDT ACPI table describes at least one domain with at least one CPU. */ static bool erdt_enabled; +static u32 erdt_max_clos; #define ERDT_VALID_VERSION 1 #define CMRC_SUPPORTED_INDEX_FN 1 @@ -57,6 +58,9 @@ bool erdt_support(int flag) if (flag == X86_FEATURE_CQM_MBM_TOTAL) return valid_subtbl_mask & BIT(ACPI_ERDT_TYPE_MMRC); + if (flag == X86_FEATURE_MBA) + return valid_subtbl_mask & BIT(ACPI_ERDT_TYPE_MARC); + return false; } @@ -257,6 +261,68 @@ int erdt_mon_read(struct rdt_domain_hdr *hdr, enum resctrl_event_id evtid, u32 r return -EIO; } +static void marc_hw_update(struct hw_param *m) +{ +} + +__init bool erdt_get_mem_config(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + struct resctrl_hw_ctrl *hw_ctrl; + struct erdt_domain_info *d; + struct acpi_erdt_marc *marc; + int max_regions, region; + unsigned int type; + + if (!erdt_cpu_has(X86_FEATURE_MBA)) + return false; + + /* Use the first domain's MARC to discover control properties. */ + d = list_first_entry_or_null(&domain_info_list, struct erdt_domain_info, entry); + if (!d || !d->marc) + return false; + + marc = d->marc; + max_regions = acpi_mrrm_max_mem_region(); + hw_res->num_closid = max(hw_res->num_closid, erdt_max_clos + 1); + + for (region = 0; region < max_regions; region++) { + for (type = RESCTRL_CTRL_REGION_TYPE_OPT; type < RESCTRL_CTRL_REGION_NR_CTRLS; type++) { + if (type == RESCTRL_CTRL_REGION_TYPE_OPT && !(marc->flags & MARC_FLAG_OPT)) + continue; + if (type == RESCTRL_CTRL_REGION_TYPE_MIN && !(marc->flags & MARC_FLAG_MIN)) + continue; + if (type == RESCTRL_CTRL_REGION_TYPE_MAX && !(marc->flags & MARC_FLAG_MAX)) + continue; + + hw_ctrl = kzalloc_obj(*hw_ctrl); + if (!hw_ctrl) + return false; + + hw_ctrl->r_ctrl.scope = RESCTRL_L3_CACHE; + hw_ctrl->r_ctrl.type = RESCTRL_CTRL_SCALAR; + hw_ctrl->r_ctrl.name = resctrl_ctrl_name_region(region, type); + INIT_LIST_HEAD(&hw_ctrl->r_ctrl.domains); + INIT_LIST_HEAD(&hw_ctrl->r_ctrl.emul); + + hw_ctrl->r_ctrl.scalar.max_bw = marc->mba_ctrl_range; + hw_ctrl->r_ctrl.scalar.min_bw = 1; + hw_ctrl->r_ctrl.scalar.bw_gran = 1; + hw_ctrl->r_ctrl.scalar.resolution = 1; + hw_ctrl->r_ctrl.scalar.tolerance = 0; + hw_ctrl->r_ctrl.scalar.scale = 1; + hw_ctrl->r_ctrl.scalar.unit = RESCTRL_CTRL_UNIT_ALL; + + hw_ctrl->hw_update = marc_hw_update; + list_add_tail(&hw_ctrl->r_ctrl.entry, &r->controls); + } + } + + r->alloc_capable = true; + + return true; +} + static void __iomem *erdt_ioremap(phys_addr_t base, u32 num_pages, const char *desc) { void __iomem *addr; @@ -699,6 +765,7 @@ static __init int enumerate_erdt_table(struct acpi_table_header *table_hdr) if (list_empty(&domain_info_list)) goto cleanup; + erdt_max_clos = erdt->max_clos; erdt_enabled = true; return 0; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 6855022bf07e..f09583c95a62 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -30,6 +30,10 @@ * @ERDT_MMIO_MARC_MIN: MARC minimum BW register base address * @ERDT_MMIO_MARC_MAX: MARC maximum BW register base address */ +#define RESCTRL_CTRL_REGION_TYPE_OPT 0 +#define RESCTRL_CTRL_REGION_TYPE_MIN 1 +#define RESCTRL_CTRL_REGION_TYPE_MAX 2 + enum erdt_mmio_type { ERDT_MMIO_RMDD_CREG, ERDT_MMIO_CMRC_BASE, @@ -324,6 +328,7 @@ static inline bool intel_handle_aet_option(bool force_off, char *tok) { return f bool erdt_support(int flag); bool erdt_cpu_has(int flag); bool erdt_enable_mon(void); +bool __init erdt_get_mem_config(struct rdt_resource *r); int erdt_get_max_rmid(void); int erdt_mon_read(struct rdt_domain_hdr *hdr, enum resctrl_event_id evtid, u32 rmid, u64 *val, bool first); -- 2.43.0