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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3b79c4533f1sm122572f8f.42.2025.07.30.14.15.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jul 2025 14:15:41 -0700 (PDT) Message-ID: <5be6d858-01e1-4c2d-bd5c-0e3385251af7@linaro.org> Date: Wed, 30 Jul 2025 23:15:40 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] arm64: dts: s32g2: Add the STM description To: Frank Li Cc: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de, s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi Procopciuc , Thomas Fossati References: <20250730195022.449894-1-daniel.lezcano@linaro.org> <20250730195022.449894-2-daniel.lezcano@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Frank, thanks for the reviews, On 30/07/2025 22:19, Frank Li wrote: > On Wed, Jul 30, 2025 at 09:50:14PM +0200, Daniel Lezcano wrote: > > I think replace all 'description' with 'node' is easy to read. Sure >> The s32g2 has a STM module containing 8 timers. Each timer has a >> dedicated interrupt and share the same clock. >> >> Add the timers STM0->STM6 description for the s32g2 SoC. The STM7 is >> not added because it is slightly different and needs an extra property >> which will be added later when supported by the driver. >> >> Signed-off-by: Daniel Lezcano >> Cc: Ghennadi Procopciuc >> Cc: Thomas Fossati >> --- >> arch/arm64/boot/dts/freescale/s32g2.dtsi | 63 ++++++++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> index ea1456d361a3..3e775d030e37 100644 >> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi >> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> @@ -503,5 +503,68 @@ gic: interrupt-controller@50800000 { >> interrupt-controller; >> #interrupt-cells = <3>; >> }; >> + >> + stm0: timer@4011c000 { > > keep order according to address. > > 4011c000 should less than 50800000. Ah, sure. I'll fix that. >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x4011c000 0x3000>; >> + interrupts = ; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + status = "disabled"; > > why not default enable. The S32G2 and S32G3 can have different variants with 2, 4, 8 Cortex-A53 and 3 or 4 Cortex-M7. We enable the same number of CPUs present on the system. AFAIU: S32G233A : 2 x Cortex-A53 S32G274A : 4 x Cortex-A53 S32G399A : 8 x Cortex-A53 S32G379A : 4 x Cortex-A53 Otherwise we would have to do the opposite, that is disable the unused ones in the s32g274a-rdb2.dts, s32g399a-rdb3.dts and other dts which include the s32g2.dtsi and s32g3.dtsi. >> + }; >> + >> + stm1: timer@40120000 { >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x40120000 0x3000>; >> + interrupts = ; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + status = "disabled"; >> + }; >> + >> + stm2: timer@40124000 { >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x40124000 0x3000>; >> + interrupts = ; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + status = "disabled"; >> + }; >> + >> + stm3: timer@40128000 { >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x40128000 0x3000>; >> + interrupts = ; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + status = "disabled"; >> + }; >> + >> + stm4: timer@4021c000 { >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x4021c000 0x3000>; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + interrupts = ; >> + status = "disabled"; >> + }; >> + >> + stm5: timer@40220000 { >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x40220000 0x3000>; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + interrupts = ; >> + status = "disabled"; >> + }; >> + >> + stm6: timer@40224000 { >> + compatible = "nxp,s32g2-stm"; >> + reg = <0x40224000 0x3000>; >> + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; >> + clock-names = "counter", "module", "register"; >> + interrupts = ; >> + status = "disabled"; >> + }; >> }; >> }; >> -- >> 2.43.0 >> -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog