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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f24-20020ac25338000000b004e8448de1c0sm5116024lfh.10.2023.03.28.06.29.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Mar 2023 06:29:39 -0700 (PDT) Message-ID: <5beab308-a114-745b-fa28-84ca0495f539@linaro.org> Date: Tue, 28 Mar 2023 15:29:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v4 3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <1679036039-27157-1-git-send-email-quic_rohiagar@quicinc.com> <1679036039-27157-4-git-send-email-quic_rohiagar@quicinc.com> From: Konrad Dybcio In-Reply-To: <1679036039-27157-4-git-send-email-quic_rohiagar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17.03.2023 07:53, Rohit Agarwal wrote: > Add support for PCIe Endpoint controller on the > Qualcomm SDX65 platform. > > Signed-off-by: Rohit Agarwal > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 084daf8..a7d8ad9 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include This should be sorted alphabetically Other than that: Reviewed-by: Konrad Dybcio Konrad > > / { > #address-cells = <1>; > @@ -293,6 +294,56 @@ > status = "disabled"; > }; > > + pcie_ep: pcie-ep@1c00000 { > + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; > + reg = <0x01c00000 0x3000>, > + <0x40000000 0xf1d>, > + <0x40000f20 0xa8>, > + <0x40001000 0x1000>, > + <0x40200000 0x100000>, > + <0x01c03000 0x3000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "addr_space", > + "mmio"; > + > + qcom,perst-regs = <&tcsr 0xb258 0xb270>; > + > + clocks = <&gcc GCC_PCIE_AUX_CLK>, > + <&gcc GCC_PCIE_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_PCIE_SLEEP_CLK>, > + <&gcc GCC_PCIE_0_CLKREF_EN>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "sleep", > + "ref"; > + > + interrupts = , > + ; > + interrupt-names = "global", "doorbell"; > + > + resets = <&gcc GCC_PCIE_BCR>; > + reset-names = "core"; > + > + power-domains = <&gcc PCIE_GDSC>; > + > + phys = <&pcie_phy>; > + phy-names = "pcie-phy"; > + > + max-link-speed = <3>; > + num-lanes = <2>; > + > + status = "disabled"; > + }; > + > pcie_phy: phy@1c06000 { > compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; > reg = <0x01c06000 0x2000>; > @@ -330,6 +381,11 @@ > #hwlock-cells = <1>; > }; > > + tcsr: syscon@1fcb000 { > + compatible = "qcom,sdx65-tcsr", "syscon"; > + reg = <0x01fc0000 0x1000>; > + }; > + > remoteproc_mpss: remoteproc@4080000 { > compatible = "qcom,sdx55-mpss-pas"; > reg = <0x04080000 0x4040>;