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Thu, 16 Apr 2026 16:29:00 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , Shuai Xue Subject: [PATCH v3 04/11] iommu: Add __iommu_group_block_device helper Date: Thu, 16 Apr 2026 16:28:33 -0700 Message-ID: <5bf2e259f80696c498cb15f40452862e4b43a295.1776381841.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002316:EE_|DM6PR12MB4354:EE_ X-MS-Office365-Filtering-Correlation-Id: ef28d998-73b5-4a74-8462-08de9c0ffc9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|7416014|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: slhvTyDS+DerOFXQhC7YfgrFZZMYmw3E+8lGrYRckARHhcYVQdw7dwX1lWIcCY1xvpyP8rjof3aj4P4FsoPz7DC6X+MUC68LX/LRiv4fhitXOlIs2hf6uyAl4sKHUTbhR7ltcaZenAUuIRxmQkYVEMqInDYJPvnrUyU8EGqLoHGHr30XV8kl2izToXmiQAEa5BL7SEJvedns7erIYhF6A2TKn2M4v4hFhkiaDMb05H1HOKGV9qjxEe3BX20m243qchRwdGG6l/wOPWRc8HcEBLYj10Q3yWXNJYEArfkvBCZRM+gXaBfime4qSuZomydJKgFcz+05DE1xARddfM2RimS48q4APMVyvKpsbXP594pV/f/grVuqgxZ1sRLvV9BV3H+aEn42HfQZsPJQQq+dYBSX2hQGvOsKQ78qX8PkuAJ+4Mv6uQq4mBj93y4i6IlU2NjHXtvQERSwbIY1CF6BF9k71iCbDYZGQwcm5K//u6w4yBKh6preX3x52sIcTCVgjpdM0p+BHp71NbE70NWUFSEgOoNlcqvGV4b2CoCDvXNP3nMWgDAK/ebWa+4BriCAVP6awdgBXPDGW5Pe9sQnofLojpSrSF1HYrsrj0DlzBJaTSL7ewWNYTj/4SvbrMNdzb26NEQzmPzlUS89iNZvLFRJs01Nwx15xDWVZCXjZ47whCsI2oYw/MZNNTYb7o7F5XSUCbb64onoLOM+x6iU1OQGcheYO1vpUHcc6RvfLoVC2dYR+5RfcuHCC1RzvIfXaGuEvNumpmGSTlhGUeCaZg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700016)(7416014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oN3rIlbDp1LkvW1b80soxbQZwmWCn2ca5fnBYNXNfkQ3Xh86dvFWR694PlYT47EMSrw+LUs9d6Ih/0GZCyaZQKLILgqscpC7/GozjXMN7b6amK/2dFumWfjyrvhcsNAwWlw8bz4moy/1CJhT9Z+gg3SiaE1Elb4kxHEmblA8O+ayS2Ui3ym1WtTjuCKJlQ7C3jGywxGtud3FgPl0RQSDUvrXX6GWzCIOVOByPEDMFCrqu/XtZqezSK2UznH5GRoqKxMu1Mm9hNd6CpkXwjxCJWoUcHMoLUgF6GlPeiU9uB8DDCCC2Dk7BUD7Z7o/PmIpuHD6eYwmVY5SRUIWyyO28dcBBSDUbNN0JZM/cjzahAHaPS5f3H/iTqhO1zML7gMTsPx0pc0218uYef0XfkdoskSZgoXaoZFaI52rnSTF4I1JI8EhgIpRZBMSlkvF05Pc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2026 23:29:20.8575 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef28d998-73b5-4a74-8462-08de9c0ffc9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002316.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4354 Move the RID/PASID blocking routine into a separate helper, which will be reused by a new function to quarantine the device but does not bother the gdev->reset_depth counter. No functional changes. Suggested-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommu.c | 99 ++++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 43 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index df23ef0a26e6c..768ac728b4cc3 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3958,6 +3958,57 @@ int iommu_replace_group_handle(struct iommu_group *group, } EXPORT_SYMBOL_NS_GPL(iommu_replace_group_handle, "IOMMUFD_INTERNAL"); +static int __iommu_group_block_device(struct iommu_group *group, + struct group_device *gdev) +{ + unsigned long pasid; + void *entry; + int ret; + + lockdep_assert_held(&group->mutex); + + /* Device might be already blocked for a quarantine */ + if (gdev->blocked) + return 0; + + ret = __iommu_group_alloc_blocking_domain(group); + if (ret) + return ret; + + /* Stage RID domain at blocking_domain while retaining group->domain */ + if (group->domain != group->blocking_domain) { + ret = __iommu_attach_device(group->blocking_domain, gdev->dev, + group->domain); + if (ret) + return ret; + } + + /* + * Update gdev->blocked upon the domain change, as it is used to return + * the correct domain in iommu_driver_get_domain_for_dev() that might be + * called in a set_dev_pasid callback function. + */ + gdev->blocked = true; + + /* + * Stage PASID domains at blocking_domain while retaining pasid_array. + * + * The pasid_array is mostly fenced by group->mutex, except one reader + * in iommu_attach_handle_get(), so it's safe to read without xa_lock. + */ + if (gdev->dev->iommu->max_pasids > 0) { + xa_for_each_start(&group->pasid_array, pasid, entry, 1) { + struct iommu_domain *pasid_dom = + pasid_array_entry_to_domain(entry); + + iommu_remove_dev_pasid(gdev->dev, pasid, pasid_dom); + } + } + + group->recovery_cnt++; + return 0; +} + /** * pci_dev_reset_iommu_prepare() - Block IOMMU to prepare for a PCI device reset * @pdev: PCI device that is going to enter a reset routine @@ -3988,8 +4039,6 @@ int pci_dev_reset_iommu_prepare(struct pci_dev *pdev) { struct iommu_group *group = pdev->dev.iommu_group; struct group_device *gdev; - unsigned long pasid; - void *entry; int ret; if (!pci_ats_supported(pdev) || !dev_has_iommu(&pdev->dev)) @@ -4003,50 +4052,14 @@ int pci_dev_reset_iommu_prepare(struct pci_dev *pdev) if (gdev->reset_depth++) return 0; - /* Device might be already blocked for a quarantine */ - if (gdev->blocked) - return 0; - - ret = __iommu_group_alloc_blocking_domain(group); - if (ret) - goto err_depth; - /* Stage RID domain at blocking_domain while retaining group->domain */ - if (group->domain != group->blocking_domain) { - ret = __iommu_attach_device(group->blocking_domain, &pdev->dev, - group->domain); - if (ret) - goto err_depth; - } - - /* - * Update gdev->blocked upon the domain change, as it is used to return - * the correct domain in iommu_driver_get_domain_for_dev() that might be - * called in a set_dev_pasid callback function. - */ - gdev->blocked = true; - - /* - * Stage PASID domains at blocking_domain while retaining pasid_array. - * - * The pasid_array is mostly fenced by group->mutex, except one reader - * in iommu_attach_handle_get(), so it's safe to read without xa_lock. - */ - if (pdev->dev.iommu->max_pasids > 0) { - xa_for_each_start(&group->pasid_array, pasid, entry, 1) { - struct iommu_domain *pasid_dom = - pasid_array_entry_to_domain(entry); - - iommu_remove_dev_pasid(&pdev->dev, pasid, pasid_dom); - } + ret = __iommu_group_block_device(group, gdev); + if (ret) { + gdev->reset_depth--; + return ret; } - group->recovery_cnt++; - return ret; - -err_depth: - gdev->reset_depth--; - return ret; + return 0; } EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_prepare); -- 2.43.0