From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01126C04AAD for ; Mon, 6 May 2019 07:25:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D1AF92082F for ; Mon, 6 May 2019 07:25:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726282AbfEFHZg (ORCPT ); Mon, 6 May 2019 03:25:36 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:46552 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725828AbfEFHZg (ORCPT ); Mon, 6 May 2019 03:25:36 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B43233A4564CE369C6FA; Mon, 6 May 2019 15:25:33 +0800 (CST) Received: from [127.0.0.1] (10.210.168.180) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Mon, 6 May 2019 15:25:30 +0800 Subject: Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events To: Florian Fainelli , References: <20190502234704.7663-1-f.fainelli@gmail.com> CC: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , "Namhyung Kim" , Will Deacon , Mark Rutland , Catalin Marinas , "moderated list:ARM PMU PROFILING AND DEBUGGING" From: John Garry Message-ID: <5c04ebac-3e3c-fa53-d287-3a602a350091@huawei.com> Date: Mon, 6 May 2019 08:25:21 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <20190502234704.7663-1-f.fainelli@gmail.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.210.168.180] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/05/2019 00:47, Florian Fainelli wrote: > The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events > up to the RC_ST_SPEC (0x91) event with the exception of: > > - L1D_CACHE_REFILL_INNER (0x44) > - L1D_CACHE_REFILL_OUTER (0x45) > - L1D_TLB_RD (0x4E) > - L1D_TLB_WR (0x4F) > - L2D_TLB_REFILL_RD (0x5C) > - L2D_TLB_REFILL_WR (0x5D) > - L2D_TLB_RD (0x5E) > - L2D_TLB_WR (0x5F) > - STREX_SPEC (0x6F) > > Create an appropriate JSON file for mapping those events and update the > mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that > file. I suppose you could have also created separate a72 and a57 folders, and used a symbolic link for the json. That would have kept the folder structure consistent and neat. > > Signed-off-by: Florian Fainelli Apart from the above: Reviewed-by: John Garry > --- > Changes in v2: > > - added a shared directory for both Cortex-A57 and A72 (Will) > - removed unsupported ARMv8 v3 events (John) > > .../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++ > tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + > 2 files changed, 181 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json > > diff --git a/tools/perf/pmu-even