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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6433a3f8767sm13141599a12.9.2025.11.18.07.02.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Nov 2025 07:02:06 -0800 (PST) Message-ID: <5c2e47f0-ba96-4433-b13e-9e819cfe2204@oss.qualcomm.com> Date: Tue, 18 Nov 2025 16:02:03 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND 2/2] drm/msm/dpu: use full scale alpha in _dpu_crtc_setup_blend_cfg() To: Dmitry Baryshkov , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20251118-dpu-rework-alpha-v1-0-293d39402b59@oss.qualcomm.com> <20251118-dpu-rework-alpha-v1-2-293d39402b59@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251118-dpu-rework-alpha-v1-2-293d39402b59@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDEyMSBTYWx0ZWRfX7NmkztPGPmFc op3kgRhUIY+I45NTLKHCT9kPus7/5eutnYJivsNOsanrbiVCJ9/lLoZG+T5TEOrXbNOQzQP+vk0 lzUfgx155ZOAuQUvElmfw8ADD/JUB2b8VEVXaF8MUizAubCf0N2QZzPwbHyxC29zUwmNnNmKIWJ EjS5Wwl4gpaOhOJYxctyajxBP6s01k6kXVFPtutxkxYSQkngwU+jSLjwzQk0q7oQ6qRwyiSVeAr tS0Z2d2EfS30ULuZvjskOdUhlgyHF7cTraDPvmKiZ2VJulRZkbsCKxnMlGWX8S4u+GtU5ASw2de L1NrpniGqacwYJCYpj2VCLNSwyfht8JlyFENoRR3iW1iuCvUnSUzkLyf0Atfe1bvG9MNjwpTY3H kSx5RyRfAdWxg663596CGSO7tLEwlg== X-Authority-Analysis: v=2.4 cv=RpTI7SmK c=1 sm=1 tr=0 ts=691c8a72 cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=08wX0RkXSFUxxunu3nEA:9 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-ORIG-GUID: aCVLFAK-eeRV0uwBD9dU4aSL2jtVvC_d X-Proofpoint-GUID: aCVLFAK-eeRV0uwBD9dU4aSL2jtVvC_d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-18_01,2025-11-18_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180121 On 11/18/25 3:51 PM, Dmitry Baryshkov wrote: > Both _dpu_crtc_setup_blend_cfg() and setup_blend_config_alpha() > callbacks embed knowledge about platform's alpha range (8-bit or > 10-bit). Make _dpu_crtc_setup_blend_cfg() use full 16-bit values for > alpha and reduce alpha only in DPU-specific callbacks. > > Signed-off-by: Dmitry Baryshkov > --- [...] > - const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); > + const_alpha = ((bg_alpha >> 8) & 0xff) | > + (((fg_alpha >> 8) & 0xff) << 16); This begs for some bitfield.h Konrad > DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); > DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); > } > @@ -160,7 +161,8 @@ dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, > if (WARN_ON(stage_off < 0)) > return; > > - const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); > + const_alpha = ((bg_alpha >> 6) & 0x3ff) | > + (((fg_alpha >> 6) & 0x3ff) << 16); > DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); > DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); > } > @@ -178,8 +180,8 @@ static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, > if (WARN_ON(stage_off < 0)) > return; > > - DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); > - DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); > + DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha >> 8); > + DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha >> 8); > DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); > } > >