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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id x22-20020aa7dad6000000b0048789661fa2sm15554559eds.66.2023.01.19.05.07.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 05:07:02 -0800 (PST) Message-ID: <5c4c6ee7-e202-716b-a3ac-04d7620b8c58@linaro.org> Date: Thu, 19 Jan 2023 15:07:01 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v3 8/8] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Content-Language: en-GB To: Abel Vesa Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "vkoul@kernel.org" , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Johan Hovold , Neil Armstrong References: <20230118005328.2378792-1-abel.vesa@linaro.org> <20230118005328.2378792-9-abel.vesa@linaro.org> <7fe0c49e-a628-8e76-8294-ab8faadb3a70@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/01/2023 01:34, Abel Vesa wrote: > On 23-01-18 06:34:41, Dmitry Baryshkov wrote: >> On 18/01/2023 02:53, Abel Vesa wrote: >>> Add the SM8550 both g4 and g3 configurations. In addition, there is a >>> new "lane shared" table that needs to be configured for g4, along with >>> the No-CSR list of resets. >>> >>> Co-developed-by: Neil Armstrong >>> Signed-off-by: Neil Armstrong >>> Signed-off-by: Abel Vesa >>> --- >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 369 +++++++++++++++++++++++ >>> 1 file changed, 369 insertions(+) >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> index bffb9e138715..6f82604bd430 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> @@ -1506,6 +1506,234 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = >>> QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), >>> }; >> >> I see that the last two patches still use 'shrd' a lot. Does this correspond >> to hw register names or is it just a vendor kernel code convention? > > It corresponds to the hw register names.. Ack, then: Reviewed-by: Dmitry Baryshkov > >> >> -- >> With best wishes >> Dmitry >> -- With best wishes Dmitry