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AJvYcCX8pctDywHIr94xisKkUOZlpJz6ydY0oLzMiPyQGL+ryomPYgZ6Ma9YnsKuCcueIvb/SStu3jmIX2SmCLKPqVeB9+uFpXlI5TvbH6ma X-Gm-Message-State: AOJu0YyUtlxKLivvL+NxUooFI3DGAoPiA2+DECNwEmD0ns1mwzm7hLTe nHO6pnHvVoVDjpfYqmapVR33KvVcz7q1IP+E3mAmbgrGvnS6gVoE5Yt80HDSj9M= X-Google-Smtp-Source: AGHT+IGZcVk2eGHvZSn6CPbma5VIP7uQjpMOrYeHbNwrT6GGHa/VN6GauQcBu3SnDNxlM8kENgnpGg== X-Received: by 2002:a50:a412:0:b0:568:1988:f699 with SMTP id u18-20020a50a412000000b005681988f699mr1802831edb.30.1710317074601; Wed, 13 Mar 2024 01:04:34 -0700 (PDT) Received: from localhost ([102.222.70.76]) by smtp.gmail.com with ESMTPSA id b20-20020aa7dc14000000b005684fa1c4dbsm3644090edu.52.2024.03.13.01.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 01:04:33 -0700 (PDT) Date: Wed, 13 Mar 2024 11:04:30 +0300 From: Dan Carpenter To: Jacky Huang Cc: linus.walleij@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, p.zabel@pengutronix.de, j.neuschaefer@gmx.net, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com Subject: Re: [PATCH v6 3/3] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver Message-ID: <5c555723-1731-40cc-b9be-a88ef617e09f@moroto.mountain> References: <20240313035719.768469-1-ychuang570808@gmail.com> <20240313035719.768469-4-ychuang570808@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240313035719.768469-4-ychuang570808@gmail.com> On Wed, Mar 13, 2024 at 03:57:19AM +0000, Jacky Huang wrote: > +static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl) > +{ > + struct ma35_pin_ctrl *ctrl = npctl->ctrl; > + struct ma35_pin_bank *bank = ctrl->pin_banks; > + int ret; > + int i; > + > + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { > + if (!bank->valid) { > + dev_warn(&pdev->dev, "bank %s is not valid\n", > + bank->np->name); > + continue; > + } > + bank->irqtype = 0; > + bank->irqinten = 0; > + bank->chip.label = bank->name; > + bank->chip.of_gpio_n_cells = 2; > + bank->chip.parent = &pdev->dev; > + bank->chip.request = ma35_gpio_core_to_request; > + bank->chip.direction_input = ma35_gpio_core_direction_in; > + bank->chip.direction_output = ma35_gpio_core_direction_out; > + bank->chip.get = ma35_gpio_core_get; > + bank->chip.set = ma35_gpio_core_set; > + bank->chip.base = -1; > + bank->chip.ngpio = bank->nr_pins; > + bank->chip.can_sleep = false; > + spin_lock_init(&bank->lock); > + > + if (bank->irq > 0) { > + struct gpio_irq_chip *girq; > + > + girq = &bank->chip.irq; > + gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip); > + girq->parent_handler = ma35_irq_demux_intgroup; > + girq->num_parents = 1; > + > + girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), > + GFP_KERNEL); > + if (!girq->parents) > + return -ENOMEM; ret = -ENOMEM; goto fail; regards, dan carpenter > + > + girq->parents[0] = bank->irq; > + girq->default_type = IRQ_TYPE_NONE; > + girq->handler = handle_level_irq; > + } > + > + ret = gpiochip_add_data(&bank->chip, bank); > + if (ret) { > + dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", > + bank->chip.label, ret); > + goto fail; > + } > + } > + return 0; > + > +fail: > + for (--i, --bank; i >= 0; --i, --bank) { > + if (!bank->valid) > + continue; > + gpiochip_remove(&bank->chip); > + } > + return ret; > +}