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Thu, 12 Nov 2026 00:24:24 -0800 (PST) Received: from [10.218.7.34] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2edb6d9baa5sm29887245ad.45.2026.11.12.00.24.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 00:24:21 -0800 (PST) Message-ID: <5c879271-6e88-4683-a280-eef292c442ba@oss.qualcomm.com> Date: Thu, 12 Nov 2026 13:54:13 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] thermal: qcom-spmi-adc-tm5-gen3: move hardirq actions into threaded handler To: Andy Shevchenko Cc: Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, kamal.wadhwa@oss.qualcomm.com, Pankaj Patil References: <20261111-adctm5_gen3_hardirq_removal-v1-1-536ed503396c@oss.qualcomm.com> Content-Language: en-US From: Jishnu Prakash In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDAzMyBTYWx0ZWRfX+Us1Qt/Bkgsc A68AjKKFK5TA2AzpIQrx/9l2spnksJljOksVvFU6TWryWpUFaJBXgK+2GUDrfJbfExvQABxw8Rm h1LIcLClK95qimcLk4nLrN/jdd5dp/s= X-Proofpoint-GUID: k8AR7V_uCxOPEYeLZoEdvdFpMqd0Qfo7 X-Proofpoint-ORIG-GUID: k8AR7V_uCxOPEYeLZoEdvdFpMqd0Qfo7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDAzMyBTYWx0ZWRfX4HpEY/HadTzO jTjN30pSj1HEZ0C/by3Oj1FEgHcgNnWlTZ16CIPOI6KosPzZhPnCpqqL4fo9yEvIGa344g5fpg/ cZheu8i7gUKq9bt6LcRaURMm/UhUW9McR5aG/FoUH+NSn05MYHR8D0Lar/ZJo5mhYDLiRuogVbo U87MharHOzSPipFVXfPPH62A5rGQkM6Uj0h8B2eY84BsuNnsAwgwJKHN7kONyesv2utCnVvbpiI ukOsIvDxeOPHn9ztAqSvBefr+b2CaD7uppj471Svfp9uQksT2iTngapCadmZwqsxLbhb45Szjd5 p16eQeGxaS6GGGOmczX7Q+kxjYvE1MgdJApHrjpfUhccBQD+W5UKaul2GhKsteBJperauAtYwRr 49DR1w492HTR6oSB4cClqHICvGaknnE1863dGBAzgf4sAA9sJrnZFKDxbzl1yhZcYarkpe+ENWw 8MhwnZLq0sNMN7WDAoA== X-Authority-Analysis: v=2.4 cv=Q9dHcI2a c=1 sm=1 tr=0 ts=6af577ba cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=9akHpOJ0G8PeWv3IIDkA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120033 Hi Andy, On 11/11/2026 7:53 PM, Andy Shevchenko wrote: > On Wed, Nov 11, 2026 at 02:12:01PM +0530, Jishnu Prakash wrote: >> adc_tm5_probe() registers the ADC_TM interrupt with both a primary >> handler and thread function (adctm5_gen3_isr/adctm5_gen3_isr_thread) >> with IRQF_ONESHOT. The primary handler calls adc5_gen3_read(), which >> takes the SPMI regmap's lock (a regular, non-raw spinlock) from hardirq >> context. With CONFIG_PROVE_LOCKING enabled, this leads to a warning >> about an attempt to take a lock in an invalid wait context: >> >> swapper/0/0 is trying to lock: >> ffff000b67201018 >> (qcom_spmi_pmic:259:(&spmi_regmap_config)->lock){....}-{3:3}, at: >> regmap_lock_spinlock+0x20/0x40 >> other info that might help us debug this: >> context-{2:2} >> locks held by swapper/0/0: 0, last CPU#0 >> stack backtrace: >> >> CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 7.4.0-rc1 #1 PREEMPT(full) >> >> Call trace: > >> check_wait_context.isra.0+0x2d8/0x380 >> __lock_acquire+0x2ec/0x840 >> lock_acquire.part.0+0xe0/0x250 >> lock_acquire+0x8c/0x1e0 > > Please, drop unneeded churn, since regmap_lock_spinlock() the rest is not needed. > It's all documented in Submitting Patches, take your time to read and study that > document. Yes, I'll trim the call stack and drop the less relevant error lines. > >> _raw_spin_lock_irqsave+0x6c/0xd8 >> regmap_lock_spinlock+0x20/0x40 >> regmap_raw_read+0x88/0x328 >> regmap_bulk_read+0x10c/0x340 >> adc5_gen3_read+0x38/0x50 [qcom_spmi_adc5_gen3] >> adctm5_gen3_isr+0x90/0x130 [qcom_spmi_adc_tm5_gen3] >> >> There is no requirement for any of the work done in the primary handler >> to run in hardirq context. Drop the primary handler and move all the >> actions in it to the threaded handler, which removes the invalid wait >> context warning. > > ... > >> -static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id) >> +static irqreturn_t adctm5_gen3_isr_thread(int irq, void *dev_id) >> { >> struct adc_tm5_gen3_chip *adc_tm5 = dev_id; >> - int ret, sdam_num; >> + int sdam_index, ret; > > Was the variable rename so important for the fix? Can we defer it to the later > cleanups, if ever needed? > >> u8 tm_status[2]; >> u8 status, val; > > ... > >> - struct adc_tm5_gen3_chip *adc_tm5 = dev_id; >> - u8 tm_status[2]; >> - int sdam_index; > > Okay, I see the reason now why it's done, but I noticed no mention of this in > the commit message. Also it's unclear which variable is used more often and > what is the real semantics of its value. Is it number or index? With all this > in mind, please at bare minimum elaborate in the commit message and, if it's > actually a number, replace the other part instead. In both adctm5_gen3_isr() and adctm5_gen3_isr_thread(), we needed a variable to store the index of the SDAM whose IRQ was triggered. We called it 'sdam_num' in adctm5_gen3_isr() and 'sdam_index' in adctm5_gen3_isr_thread(). In the rest of the file, it is called 'sdam_index', so ideally that same name should have been used in adctm5_gen3_isr() too, as it is more accurate than 'sdam_num'. As I mentioned at the end of the commit message, I just meant to drop adctm5_gen3_isr() and expand adctm5_gen3_isr_thread() to include the actions formerly done in adctm5_gen3_isr(), but I see the diff makes it look more like I modified adctm5_gen3_isr() into adctm5_gen3_isr_thread() with a variable rename, which is a bit misleading. I can add a line in the commit message to emphasize that 'sdam_num' is the same as 'sdam_index' if you think it helps. Thanks, JIshnu >