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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b86fc303d7esm1399217166b.2.2026.01.14.05.47.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jan 2026 05:47:59 -0800 (PST) Message-ID: <5cd1f4f5-808d-46cf-a44a-ee5428987727@oss.qualcomm.com> Date: Wed, 14 Jan 2026 14:47:57 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Pankaj Patil , Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com> <20260112-upstream_v3_glymur_introduction-v4-3-8a0366210e02@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE0MDExNSBTYWx0ZWRfXxOAbXXmhOL/R SHUC188CbOryStaziZpjFTMP3CyA4y2ck++9azZdPKIQ27zg0tCgtq4n5BcBWBbHvslt5CeWloX MPOcEobHHD0ixe7fBsNM+TkmtwP6FnUP1U0nrmfAzsoRLEfaN2SSeBOHVAHDGjDdfopcMzPScDj x4cLOkggj0J8M6SUy5U0mmklyQmEsCPtImW7es8BnBp8YLD8bmPDTOes+Et+EaWtrny1v+2bQaO k643b9psP9EBrI8K6dZDs16LVmVhs0/b4N+z5g6i3HQHNRnMBrKJQpQRlTHzUMpHfjdnjuOq8S+ 4QCUblzhVNJKMaFOr16gwS2bGwvlHHULp8QT0O6I2gN91qy22+xoe2mzdrmCqqP7EPtr5vjrJHC Do082U73JImiCdZYptZ7VDuBXHPRC5YdoMyw9xfxF2HSM6HgrjWDyZfYpGrelCLQ93MrQRbEQ32 C+/ukZu/diFSWEztljg== X-Authority-Analysis: v=2.4 cv=BZnVE7t2 c=1 sm=1 tr=0 ts=69679e91 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=5tyqGv89VatObklNbhcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: 2Q-DiLFIeJeziQuThb7dgBf3VMyfT8UC X-Proofpoint-GUID: 2Q-DiLFIeJeziQuThb7dgBf3VMyfT8UC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-14_04,2026-01-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601140115 On 1/14/26 11:29 AM, Pankaj Patil wrote: > On 1/14/2026 9:47 AM, Bjorn Andersson wrote: >> On Mon, Jan 12, 2026 at 05:52:36PM +0530, Pankaj Patil wrote: >>> Introduce the base device tree support for Glymur – Qualcomm's >>> next-generation compute SoC. The new glymur.dtsi describes the core SoC >>> components, including: >>> >>> - CPUs and CPU topology >>> - Interrupt controller and TLMM >>> - GCC,DISPCC and RPMHCC clock controllers >>> - Reserved memory and interconnects >>> - APPS and PCIe SMMU and firmware SCM >>> - Watchdog, RPMHPD, APPS RSC and SRAM >>> - PSCI and PMU nodes >>> - QUPv3 serial engines >>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS >>> - PDP0 mailbox, IPCC and AOSS >>> - Display clock controller >>> - SPMI PMIC arbiter with SPMI0/1/2 buses >>> - SMP2P nodes >>> - TSENS and thermal zones (8 instances, 92 sensors) >>> >>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, >>> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur >>> >>> Enabled PCIe controllers and associated PHY to support boot to >>> shell with nvme storage, >>> List of PCIe instances enabled: >>> >>> - PCIe3b >>> - PCIe4 >>> - PCIe5 >>> - PCIe6 >>> >> >> Why didn't you run "make qcom/glymur-crd.dtb CHECK_DTBS=1" before >> sending patches to the mailing list?! >> >> It would taken you 30 seconds to conclude that I can't do anything with >> these patches. >> >> Regards, >> Bjorn > > I've ran the bindings check, dt-bindings specified as dependencies will fix the errors > Additionally, I'll drop qup-memory from interconnects for serial and spi in next rev, > which cause the bindings errors, this was missed The SPI flavor of QUPs is definitely DMA-capable and I don't see how it could error out with the current bindings definition Konrad