From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
To: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Srinivasa Rao Mandadapu <srivasam@codeaurora.com>,
agross@kernel.org, bjorn.andersson@linaro.org,
lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz,
tiwai@suse.com, rohitkr@codeaurora.org,
linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
swboyd@chromium.org, judyhsiao@chromium.org
Cc: Venkata Prasad Potturu <potturu@codeaurora.org>
Subject: Re: [PATCH v7 03/10] ASoC: qcom: Add register definition for codec rddma and wrdma
Date: Fri, 3 Dec 2021 20:59:31 +0530 [thread overview]
Message-ID: <5cea3676-f8e8-b6e6-84f9-685e7625cb95@codeaurora.org> (raw)
In-Reply-To: <87df2562-f9c0-188d-601b-d9c896b3719e@linaro.org>
On 12/3/2021 6:58 PM, Srinivas Kandagatla wrote:
Thanks for your time Srini!!!
>
> On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> This patch adds register definitions for codec read dma and write dma
>> lpass interface.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>
> Overall the patch LGTM,
> but for bisectablity reasons, pleas make sure these macros
>
> is_rxtx_cdc_dma_port()
> is_cdc_dma_port()
>
> to be avaiable in this patch.
Okay. Will change accordingly.
>
> Once that is fixed you could add my
>
> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>
> --srini
>
>
>> ---
>> sound/soc/qcom/lpass-lpaif-reg.h | 127
>> +++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 121 insertions(+), 6 deletions(-)
>>
>> diff --git a/sound/soc/qcom/lpass-lpaif-reg.h
>> b/sound/soc/qcom/lpass-lpaif-reg.h
>> index 2eb03ad..6d9d9d1 100644
>> --- a/sound/soc/qcom/lpass-lpaif-reg.h
>> +++ b/sound/soc/qcom/lpass-lpaif-reg.h
>> @@ -74,6 +74,21 @@
>> #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4,
>> (port))
>> #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC,
>> (port))
>> +/* LPAIF RXTX IRQ */
>> +#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
>> + (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride *
>> (port))
>> +
>> +#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v,
>> 0x0, port)
>> +#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v,
>> 0x4, port)
>> +#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v,
>> 0xC, port)
>> +
>> +/* LPAIF VA IRQ */
>> +#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
>> + (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
>> +
>> +#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
>> +#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4,
>> port)
>> +#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC,
>> port)
>> #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
>> ((v->hdmi_irq_reg_base) + (addr))
>> @@ -139,12 +154,112 @@
>> (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
>> LPAIF_WRDMA##reg##_REG(v, chan))
>> -#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, CTL, dai_id)
>> -#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, BASE, dai_id)
>> -#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id)
>> __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
>> -#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, CURR, dai_id)
>> -#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, PER, dai_id)
>> -#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id)
>> __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
>> +#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
>> +#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
>> +#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
>> +#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
>> +#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
>> +#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
>> +
>> +#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ? \
>> + (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride *
>> (chan)) : \
>> + (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
>> +
>> +#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ? \
>> + (v->rxtx_wrdma_reg_base + (addr) + \
>> + v->rxtx_wrdma_reg_stride * (chan -
>> v->rxtx_wrdma_channel_start)) : \
>> + (v->va_wrdma_reg_base + (addr) + \
>> + v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
>> +
>> +#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ?
>> LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
>> + LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
>> +
>> +#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ?
>> LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
>> + LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
>> +
>> +#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
>> + ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
>> + __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
>> + __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
>> +
>> +#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
>> + ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
>> + LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
>> + LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
>> +
>> +#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
>> + LPAIF_DMACTL_REG(v, chan, dir, dai_id))
>> #define LPAIF_DMACTL_BURSTEN_SINGLE 0
>> #define LPAIF_DMACTL_BURSTEN_INCR4 1
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2021-12-03 15:29 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 15:43 [PATCH v7 00/10] Add support for audio on SC7280 based targets Srinivasa Rao Mandadapu
2021-12-02 15:43 ` [PATCH v7 01/10] ASoC: qcom: Move lpass_pcm_data structure to lpass header Srinivasa Rao Mandadapu
2021-12-02 15:43 ` [PATCH v7 02/10] ASoC: qcom: lpass: Add dma fields for codec dma lpass interface Srinivasa Rao Mandadapu
2021-12-02 15:43 ` [PATCH v7 03/10] ASoC: qcom: Add register definition for codec rddma and wrdma Srinivasa Rao Mandadapu
2021-12-03 13:28 ` Srinivas Kandagatla
2021-12-03 15:29 ` Srinivasa Rao Mandadapu [this message]
2021-12-02 15:43 ` [PATCH v7 04/10] ASoC: qcom: Add lpass CPU driver for codec dma control Srinivasa Rao Mandadapu
2021-12-03 13:29 ` Srinivas Kandagatla
2021-12-02 15:43 ` [PATCH v7 05/10] ASoC: qcom: Add helper function to get dma control and lpaif handle Srinivasa Rao Mandadapu
2021-12-02 15:43 ` [PATCH v7 06/10] ASoC: qcom: Add support for codec dma driver Srinivasa Rao Mandadapu
2021-12-03 13:29 ` Srinivas Kandagatla
2021-12-03 15:34 ` Srinivasa Rao Mandadapu
2021-12-02 15:43 ` [PATCH v7 07/10] ASoC: qcom: Add regmap config " Srinivasa Rao Mandadapu
2021-12-03 13:29 ` Srinivas Kandagatla
2021-12-02 15:43 ` [PATCH v7 08/10] ASoC: dt-bindings: Add SC7280 lpass cpu bindings Srinivasa Rao Mandadapu
2021-12-02 20:03 ` Rob Herring
2021-12-02 15:43 ` [PATCH v7 09/10] ASoC: qcom: lpass-sc7280: Add platform driver for lpass audio Srinivasa Rao Mandadapu
2021-12-03 13:29 ` Srinivas Kandagatla
2021-12-02 15:43 ` [PATCH v7 10/10] ASoC: qcom: SC7280: Update config for building codec dma drivers Srinivasa Rao Mandadapu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5cea3676-f8e8-b6e6-84f9-685e7625cb95@codeaurora.org \
--to=srivasam@codeaurora.org \
--cc=agross@kernel.org \
--cc=alsa-devel@alsa-project.org \
--cc=bgoswami@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=judyhsiao@chromium.org \
--cc=lgirdwood@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=perex@perex.cz \
--cc=plai@codeaurora.org \
--cc=potturu@codeaurora.org \
--cc=robh+dt@kernel.org \
--cc=rohitkr@codeaurora.org \
--cc=srinivas.kandagatla@linaro.org \
--cc=srivasam@codeaurora.com \
--cc=swboyd@chromium.org \
--cc=tiwai@suse.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®