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([2600:8803:e7e4:1d00:f7b4:dfbd:5110:c59d]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3196d24601csm373137fac.2.2025.08.30.10.27.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Aug 2025 10:27:43 -0700 (PDT) Message-ID: <5d03a10f-5281-49a7-b578-b45d7b69209c@baylibre.com> Date: Sat, 30 Aug 2025 12:27:42 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/15] dt-bindings: iio: adc: adi,ad4030: Add adi,dual-data-rate To: Marcelo Schmitt , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-spi@vger.kernel.org Cc: jic23@kernel.org, Michael.Hennerich@analog.com, nuno.sa@analog.com, eblanc@baylibre.com, andy@kernel.org, corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org, Jonathan.Cameron@huawei.com, andriy.shevchenko@linux.intel.com, ahaslam@baylibre.com, sergiu.cuciurean@analog.com, marcelo.schmitt1@gmail.com References: Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 8/29/25 7:44 PM, Marcelo Schmitt wrote: > On echo and host clock modes, AD4030 and similar devices can do two data > bit transitions per clock cycle per active lane. Document how to specify > dual data rate (DDR) feature for AD4030 series devices in device tree. > I don't think this needs to be in the devicetree. Dual data rate doesn't depend on wiring, it only depends on if the SPI controller supports it or not. The core SPI code in Linux already has dtr_caps for SPI controllers to indicate that they have DDR support. So an ADC driver can just check this flag to see if the controller supports it. No devicetree flags required.