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[188.32.106.30]) by smtp.gmail.com with ESMTPSA id b7-20020a056512024700b004849077e2c6sm2724787lfo.82.2022.07.13.02.50.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jul 2022 02:50:00 -0700 (PDT) Message-ID: <5d14cf64-46b7-dc37-bbb8-dd6be82d06af@gmail.com> Date: Wed, 13 Jul 2022 12:49:58 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 2/2] lib/string.c: Optimize memchr() Content-Language: en-US To: David Laight , 'Yu-Jen Chang' Cc: "andy@kernel.org" , "akinobu.mita@gmail.com" , Ching-Chun Huang , "linux-kernel@vger.kernel.org" References: <20220710142822.52539-1-arthurchang09@gmail.com> <20220710142822.52539-3-arthurchang09@gmail.com> <3a1b50d2-a7aa-3e89-56fe-5d14ef9da22f@gmail.com> <48db247e-f6fd-cb4b-7cc5-455bf26bb153@gmail.com> <49a8be9269ee47de9fc2d0d7f09eb0b1@AcuMS.aculab.com> From: Andrey Semashev In-Reply-To: <49a8be9269ee47de9fc2d0d7f09eb0b1@AcuMS.aculab.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/13/22 12:39, David Laight wrote: > From: Yu-Jen Chang >> Sent: 12 July 2022 15:59 > ... >>> I think you're missing the point. Loads at unaligned addresses may not >>> be allowed by hardware using conventional load instructions or may be >>> inefficient. Given that this memchr implementation is used as a fallback >>> when no hardware-specific version is available, you should be >>> conservative wrt. hardware capabilities and behavior. You should >>> probably have a pre-alignment loop. >> >> Got it. I add pre-alignment loop. It aligns the address to 8 or 4bytes. > > That should be predicated on !HAS_EFFICIENT_UNALIGNED_ACCESS. > > ... >> for (; p <= end - 8; p += 8) { >> val = *(u64*)p ^ mask; >> if ((val + 0xfefefefefefefeffull) >> & (~val & 0x8080808080808080ull)) >> break; > > I would add a couple of comments, like: > // Convert to check for zero byte. > // Standard check for a zero byte in a word. > (But not the big 4 line explanation you had. > > It is also worth looking at how that code compiles > on 32bit arch that don't have a carry flag. > That is everything based on MIPS, including riscv. It may be worth looking at how glibc does it: https://sourceware.org/git/?p=glibc.git;a=blob;f=string/memchr.c;h=422bcd0cd646ea46711a57fa3cbdb8a3329fc302;hb=refs/heads/release/2.35/master#l46 They do use 32-bit words on 32-bit targets and 64-bit on 64-bit ones. I think memchr in the kernel should follow this.