From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B960FC433F5 for ; Tue, 5 Apr 2022 05:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229573AbiDEFHe (ORCPT ); Tue, 5 Apr 2022 01:07:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229639AbiDEFH1 (ORCPT ); Tue, 5 Apr 2022 01:07:27 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39B71483B8; Mon, 4 Apr 2022 22:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649135126; x=1680671126; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=LkxzEX1anG4s/wmWN5T1Ru9TpO+y0pigaqRc6/MAp74=; b=hkTEbrENBz2DxmOhLmhj3UOKp9+PNnIyKTw16MyxdGO3IFoKVhfyVPP2 47Pt66O04n+IgBNKsYqNzpx6/fjakkM3RKQfcZZD2Pwlhvf+IQ0Q4GRFd ThV9O3/9affKK34oi4Y2IhMikdT/so/XcCpMLPwwVavmpi6Q6bY1SRkGI k=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 04 Apr 2022 22:05:26 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 22:05:10 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 4 Apr 2022 22:05:10 -0700 Received: from [10.216.10.223] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 4 Apr 2022 22:05:06 -0700 Message-ID: <5d2f23a5-e8a9-6be1-cc91-0a80bad68f3a@quicinc.com> Date: Tue, 5 Apr 2022 10:35:03 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node Content-Language: en-US To: Stephen Boyd , , , , , , , , , CC: Venkata Prasad Potturu References: <1647863959-3289-1-git-send-email-quic_srivasam@quicinc.com> <1647863959-3289-4-git-send-email-quic_srivasam@quicinc.com> From: Srinivasa Rao Mandadapu Organization: Qualcomm In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/22/2022 1:56 AM, Stephen Boyd wrote: > Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:19) >> Add LPASS LPI pinctrl node required for Audio functionality on sc7280 >> based platforms. >> >> Signed-off-by: Srinivasa Rao Mandadapu >> Co-developed-by: Venkata Prasad Potturu >> Signed-off-by: Venkata Prasad Potturu >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 147 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 8d8cec5..499299a 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1987,6 +1987,153 @@ >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + lpass_tlmm: pinctrl@33c0000 { >> + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; >> + reg = <0 0x33c0000 0x0 0x20000>, >> + <0 0x3550000 0x0 0x10000>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + gpio-ranges = <&lpass_tlmm 0 0 15>; >> + >> + #clock-cells = <1>; >> + >> + dmic01_active: dmic01-active { >> + clk { >> + pins = "gpio6"; >> + function = "dmic1_clk"; >> + drive-strength = <8>; >> + output-high; > The rule of thumb is that drive strength, output/input, and bias > properties should be in the board file, because the board layout decides > the drive strength, the output level could be inverted on the board, and > the biasing could be done externally (or not) via pullup/pulldowns on > the net. The gpio driver should be able to make pins into inputs > automatically when the gpio is requested and used so having input or > output is typically wrong and should be handled by the consumer driver. Okay. will re arrange accordingly and remove output-high property. > >> + }; >> + >> + data { >> + pins = "gpio7"; >> + function = "dmic1_data"; > So in the end I'd expect to only see pins and function properties in the > SoC dtsi file. Okay. > >> + drive-strength = <8>; >> + }; >> + }; >> + >> + dmic01_sleep: dmic01-sleep { >> + clk { >> + pins = "gpio6"; >> + function = "dmic1_clk";