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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c16609e1b6sm21738805ad.38.2026.06.03.04.03.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Jun 2026 04:03:19 -0700 (PDT) Message-ID: <5d6ecdf7-1987-4ecf-ad59-06595742cc8f@gmail.com> Date: Wed, 3 Jun 2026 19:03:16 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] spi: Add Nuvoton MA35D1 QSPI controller support To: Mark Brown Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260603043551.1062112-1-cwweng.linux@gmail.com> <20260603043551.1062112-3-cwweng.linux@gmail.com> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Mark, Thanks for the review. I will address these in v2: - add "depends on ARCH_MA35 || COMPILE_TEST" to the Kconfig entry; - convert the file header to // comments; - split the low-level CS register update from the SPI core .set_cs()   callback, and make the spi-mem direct CS path handle SPI_CS_HIGH   explicitly; - use op->max_freq for spi-mem operations instead of spi->max_speed_hz. I will also fix the subject lines in the next version. Best regards, Chi-Wen Weng Mark Brown 於 2026/6/3 下午 05:30 寫道: > On Wed, Jun 03, 2026 at 12:35:51PM +0800, Chi-Wen Weng wrote: > >> +config SPI_MA35D1_QSPI >> + tristate "Nuvoton MA35D1 QSPI Controller" >> + help >> + This driver provides support for Nuvoton MA35D1 >> + QSPI controller in master mode. >> + > Other drivers for this SoC seem to have ARCH_MA35 || COMPILE_TEST? > >> @@ -0,0 +1,579 @@ >> +// SPDX-License-Identifier: GPL-2.0-or-later >> +/* >> + * Nuvoton MA35D1 QSPI controller driver >> + * >> + * Copyright (c) 2026 Nuvoton Technology Corp. >> + * Author: Chi-Wen Weng >> + */ > Please make the entire comment a C++ one so things look more > intentional. > >> +static void nuvoton_qspi_set_cs(struct spi_device *spi, bool enable) >> +{ >> + struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); >> + unsigned int cs = spi_get_chipselect(spi, 0); >> + u32 mask; >> + u32 val; >> + >> + if (cs == 0) >> + mask = NUVOTON_QSPI_SSCTL_SS0_MASK; >> + else >> + mask = NUVOTON_QSPI_SSCTL_SS1_MASK; >> + >> + val = nuvoton_qspi_read(qspi, NUVOTON_QSPI_SSCTL_OFFSET); >> + >> + /* SPI core passes enable=true when CS is asserted (typically active-low) */ >> + if (enable) >> + val |= mask; >> + else >> + val &= ~mask; >> + >> + nuvoton_qspi_write(qspi, val, NUVOTON_QSPI_SSCTL_OFFSET); >> +} > Note that the core deals with SPI_CS_HIGH, the driver doesn't need to... > >> +static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, >> + const struct spi_mem_op *op) >> +{ >> + struct spi_device *spi = mem->spi; >> + struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); >> + u8 addr[4]; >> + int ret; >> + int i; >> + >> + ret = nuvoton_qspi_setup_transfer(spi, NULL); >> + if (ret) >> + return ret; > This uses spi->max_speed_hz but spi_mem configures p->max_freq which you > should use (it might be lower). > >> + >> + nuvoton_qspi_set_cs(spi, true); > ...except where you're calling in directly at which point the driver > needs to figure this out.