Re: [PATCH] arm64: dts: imx8mm: Add UART1 UART1_DCE_RTS/CTS pin's mux option #4

[Schrempf Frieder <frieder.schrempf@kontron.de>]

Hello Michael,

On 01.01.20 17:34, Michael Trimarchi wrote:
> According to i.MX8MM reference manual Rev.2, 08/2019. According
> to the manual the two pins has associated daisy chain so input
> register and input value should be set too

I have sent a patch that covers this and it was already applied to 
linux-next. See [1].

What bothers me is that you have different values for 
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B.

Could you double check those values to find out if my version or your 
version is correct? Did you already test these settings on real hardware 
(I didn't so far)?

Thanks,
Frieder

[1]: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit?h=next-20200107&id=2728c4a124a10e96891e93748471f8e2398c266f

> 
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> ---
>   arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
> index cffa8991880d..62d16b1d7c5b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
> @@ -438,10 +438,12 @@
>   #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
>   #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
>   #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B                              0x1B8 0x420 0x4F0 0x4 0x2
>   #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
>   #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
>   #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
>   #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B                              0x1BC 0x424 0x4F0 0x4 0x2
>   #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
>   #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
>   #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
>