From: "Raz Ben-Jehuda(caro)" <raziebe@gmail.com>
To: "Arjan van de Ven" <arjan@infradead.org>
Cc: "Linux Kernel" <linux-kernel@vger.kernel.org>
Subject: Re: irq/0/smp_affinity =3 doesn't seem to work
Date: Tue, 5 Dec 2006 21:14:56 +0200 [thread overview]
Message-ID: <5d96567b0612051114m21266529v779e34ffc492fc5e@mail.gmail.com> (raw)
In-Reply-To: <1165336346.3233.382.camel@laptopd505.fenrus.org>
On 12/5/06, Arjan van de Ven <arjan@infradead.org> wrote:
> On Tue, 2006-12-05 at 18:30 +0200, Raz Ben-Jehuda(caro) wrote:
> > hello.
> >
> > I have a dual cpu AMD machine, I noticed that
> > only one timer0 is working in /proc/interrutps.
> > setting proc/irq/0/smp_affinity to 3 does make
> > any difference.
>
> if you set it to 3 then the chipset gets to decide where the irq goes.
> Many decide to send it to the first cpu.
>
> (not that it matters, the timer is so low frequency that it can go
> anywhere without problems)
>
> --
> if you want to mail me at work (you don't), use arjan (at) linux.intel.com
> Test the interaction between Linux and your BIOS via http://www.linuxfirmwarekit.org
>
>
thanks Arjan.
Yet something is not clear to me.
To the best of my knowledge , each cpu run its own schedule routine.
So, if only cpu0 gets timer0 interrupts, how does cpu1
gets to run the schedule function ?
what interrupts cpu1' current task ?
raz
next prev parent reply other threads:[~2006-12-05 19:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-12-05 16:30 Raz Ben-Jehuda(caro)
2006-12-05 16:32 ` Arjan van de Ven
2006-12-05 19:14 ` Raz Ben-Jehuda(caro) [this message]
2006-12-05 19:19 ` Arjan van de Ven
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