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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?82c79eNyiBQimPSt3wafRD+iOEAX3DLDjIatCb6wrbQwKBo0QdT02OxWG4I+?= =?us-ascii?Q?HwqkHxQGAAI9Xs44c3vCZ/AA6ioaizgO2Hzl1FqDV8hyB+14kVvcc6uhtnsQ?= =?us-ascii?Q?FeMqPFL/w1jV0e+jzG3mKmVnD+cmGDvpb8Lg61u1gQPaRfdfIElXRhNiZLpJ?= =?us-ascii?Q?E0oScbSNFoMhItruhyWEeANkzI2qiebPa0DsOPth7FYlIepkJD1KaIXDmWyJ?= =?us-ascii?Q?zJDo8rVYK7X5QpD2hKYgUGi+qA1ohlaMVjATmmuV3udN8RbqJglbGJV8qtQ0?= =?us-ascii?Q?j9mUM9gp9tM43pgnnrL4GUiDeseEfhNAqS/Bz85LZ3MM4JJXwBDWx2X4015m?= =?us-ascii?Q?XwhknmQUJRndCicuwco+yo1hvdmd1NGas6oePYL60y8e+M5S2/9d6IGO5AJ1?= =?us-ascii?Q?wI5BBoWqKPWfrQbgtk0fOgd2Y2w6RU9iRTTxxJnFkBCNLmZ1SYBUN91ryaIc?= =?us-ascii?Q?uc4p2DOSgVc6Cg2MNXxT0DMydpdJ+mvPh0LZ7rqT9DVfilraqIG+g4vXyWbG?= =?us-ascii?Q?WNe3NborpWFc4ei63CdK4QZYPtwxDhHeN4ADNxJoGStYjF0iMeWyfXoLV6DM?= =?us-ascii?Q?E2vilMEBwLlL+WpUXhCBYxE4fHPkqYeUHRjW2ES07jjWU2FM+ENc2UJ9C8qg?= =?us-ascii?Q?7Gb21VB8dbsYCeZeGMdHzIqtKEVLssDvxOWpxiW7lcedCKoa6L45ORvlJST1?= =?us-ascii?Q?toVVcJQzEfPewDSVxmJ84EHQSJdQeK5I+JP61cC1tU/5pqGD5Okn35gZgKlK?= =?us-ascii?Q?5ul3fDtc3HSBcHrbGVG7TxpPOLZQebwi5pDsyfv4z4WDHrQ+P1D+JZY1p5Hl?= =?us-ascii?Q?j9BtigHNvtiRd3TvtEJnImxEp2RU/rmhyEZ7GDPf3gfToFdCbaZmgdZ8hgjT?= =?us-ascii?Q?lksd+nIhLiTaKGsr09mcBVzn4xy6ZKsjzs9PZm9EB49y1nnwo9w7ze4BKHYp?= =?us-ascii?Q?sxhjYB9gBJXG8+1B5fSt5B0jbGlzvi+G6T944lojfY1p+qdTQViKuV5q/OHC?= =?us-ascii?Q?y9Q4eX4AhFsZ/A7phJt0XR4Fdv7kAyyIdHLTZ2po8oqgkgKzxy6hLjNUPrkK?= =?us-ascii?Q?wgkq8ok5NwiuJQELYuKvnUnEvlrFEHGE78R0gEUECiigUXrP23O376uM008S?= =?us-ascii?Q?AU9G0atv9aTaq3Vib2zii3hL8Ne4YQ5REKu9NccMB19hCmzOvj0fo+ZxaRyb?= =?us-ascii?Q?K91drPgEvEkaQeVndEAXJsawJc5mm8wQkxE6WRXpbjL7Z9jLmI6x609Pj3/p?= =?us-ascii?Q?HH9OpYtAeNJseXYz2c0MlhgZBQ8FFN79cOZ3/e/PbjDtW7oUtYqDFO6HeIEQ?= =?us-ascii?Q?ayz5QMwhwXFob6tJFPHBQ3RdGkEnlPkH6u5Am37/OfaweHsC5BhRSIvldsSg?= =?us-ascii?Q?5AfHie9TUfsYgR2cY/fWtoR9QAPHNxbKmKolELVe1hhrKFxXw89UCp6fpcT+?= =?us-ascii?Q?vzVgnQiyxmUJNVgf3xXFkoXY9YfeqxC4HO6pmtHTZ+dTGZpQ0rSOQF3hfjdV?= =?us-ascii?Q?OQCiKlyzdT7S6KmO0kluvhLFnyV/dJFM+bM5OJqrb+mGk/nvjW98HMhCo64l?= =?us-ascii?Q?cZoidKdLdaWCuP54uKoPdZLxon9vdsgBkDv5KeqndNejBi6CY48PSXrhTnTs?= =?us-ascii?Q?eQ191nrWLRABXfddr9ldtt4=3D?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3637143f-f829-4cbe-21af-08dbd68a6708 X-MS-Exchange-CrossTenant-AuthSource: DM5PR0102MB3590.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2023 01:16:53.1673 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ETDJ4h03AuVbaZjRezqaPiqKnU4nIvLCcy3MKxaBDWFfWWb7wsCG9EE2TVh4RtUFp+Lkzdj5umMCzUAzynizndF0jueN4avUp2Xtiuu0ZrUM/2GM+LGZqhLUmH19AxEr X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR01MB6527 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On Thu, 26 Oct 2023, Marc Zyngier wrote: > On Wed, 25 Oct 2023 21:08:15 +0100, > Ilkka Koskinen wrote: >> >> The upper 32 bits of PMCEID[n] registers are used to describe whether >> architectural and microarchitectural events in range 0x4000-0x401f >> exist. Due to disgarding the bits, the driver made the events invisible, >> even if they existed. >> >> Fixes: df29ddf4f04b ("arm64: perf: Abstract system register accesses away") >> Reported-by: Carl Worth >> Signed-off-by: Ilkka Koskinen >> --- >> arch/arm64/include/asm/arm_pmuv3.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h >> index 18dc2fb3d7b7..3e92b7cb57a4 100644 >> --- a/arch/arm64/include/asm/arm_pmuv3.h >> +++ b/arch/arm64/include/asm/arm_pmuv3.h >> @@ -126,12 +126,12 @@ static inline void write_pmuserenr(u32 val) >> write_sysreg(val, pmuserenr_el0); >> } >> >> -static inline u32 read_pmceid0(void) >> +static inline u64 read_pmceid0(void) >> { >> return read_sysreg(pmceid0_el0); >> } >> >> -static inline u32 read_pmceid1(void) >> +static inline u64 read_pmceid1(void) >> { >> return read_sysreg(pmceid1_el0); >> } > > This is necessary, but not sufficient. You also need to update the > corresponding 32bit accessors to match this behaviour. Something along > the lines of the patch below > > M. Thanks! I'll add your code to the second version. Cheers, Ilkka > > diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h > index 72529f5e2bed..90841cb7ce43 100644 > --- a/arch/arm/include/asm/arm_pmuv3.h > +++ b/arch/arm/include/asm/arm_pmuv3.h > @@ -23,6 +23,8 @@ > #define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0) > #define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1) > #define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2) > +#define PMCEID2 __ACCESS_CP15(c9, 0, c14, 4) > +#define PMCEID3 __ACCESS_CP15(c9, 0, c14, 5) > #define PMMIR __ACCESS_CP15(c9, 0, c14, 6) > #define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7) > > @@ -205,16 +207,6 @@ static inline void write_pmuserenr(u32 val) > write_sysreg(val, PMUSERENR); > } > > -static inline u32 read_pmceid0(void) > -{ > - return read_sysreg(PMCEID0); > -} > - > -static inline u32 read_pmceid1(void) > -{ > - return read_sysreg(PMCEID1); > -} > - > static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} > static inline void kvm_clr_pmu_events(u32 clr) {} > static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) > @@ -231,6 +223,7 @@ static inline void kvm_vcpu_pmu_resync_el0(void) {} > > /* PMU Version in DFR Register */ > #define ARMV8_PMU_DFR_VER_NI 0 > +#define ARMV8_PMU_DFR_VER_V3P1 0x4 > #define ARMV8_PMU_DFR_VER_V3P4 0x5 > #define ARMV8_PMU_DFR_VER_V3P5 0x6 > #define ARMV8_PMU_DFR_VER_IMP_DEF 0xF > @@ -251,4 +244,24 @@ static inline bool is_pmuv3p5(int pmuver) > return pmuver >= ARMV8_PMU_DFR_VER_V3P5; > } > > +static inline u64 read_pmceid0(void) > +{ > + u64 val = read_sysreg(PMCEID0); > + > + if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1) > + val |= (u64)read_sysreg(PMCEID2) << 32; > + > + return val; > +} > + > +static inline u64 read_pmceid1(void) > +{ > + u64 val = read_sysreg(PMCEID1); > + > + if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1) > + val |= (u64)read_sysreg(PMCEID3) << 32; > + > + return val; > +} > + > #endif > > -- > Without deviation from the norm, progress is not possible. >