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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Jv38bc4C c=1 sm=1 tr=0 ts=6916e93f cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=_Uc-8ieBvFDwtx1LFMkA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA2NiBTYWx0ZWRfX1dd6me13bDZf H3pKrx/ijzE1l/UNuNbriJdxG3GX15XX+vlNruL+yBQpP6ItDO49uaC/CzmeRvzQDAXrKCSfglT qlolPGmNwxTsPpoTfNmcnlOwlSixhicQhQkbKusrOWRCUlS6vN7nFDlfihhIQi/Ikk8i42F3C1v MQGPyWHaU+2+H7zryk0/SEtb3l0SxgqH9ufSaFolgFI+20drDFl1WqwKBdWQgsv4usBYeDD9RmQ IEC4yI+4cAmROo+AwDNXIXXVgbRQneDe9Wa6lXvJMChEqyfnMjpdFadOMbZ/3JsGjJtjm0bB9T6 KqWujTt8k79h+heaDaLBV0h2jSN5hIH2bETvhyur/d4XgFPz45aFseJfhuH0rDOJe3Q7bXHVVpO K6AJmYbLDCqCCluWnslqSlNzHlKHgQ== X-Proofpoint-ORIG-GUID: YOrvo2soe6ydSjY--kuX6VgEQVxt0b_e X-Proofpoint-GUID: YOrvo2soe6ydSjY--kuX6VgEQVxt0b_e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_02,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140066 On 11/10/2025 8:09 PM, Bjorn Andersson wrote: > On Mon, Nov 10, 2025 at 12:08:01PM +0530, Sarthak Garg wrote: >> According to the hardware programming guide, the clock frequency must >> remain below 52MHz during the transition to HS400 mode. >> >> However,in the current implementation, the timing is set to HS400 (a >> DDR mode) before adjusting the clock. This causes the clock to double >> prematurely to 104MHz during the transition phase, violating the >> specification and potentially resulting in CRC errors or CMD timeouts. >> >> This change ensures that clock doubling is avoided during intermediate >> transitions and is applied only when the card requires a 200MHz clock >> for HS400 operation. >> >> Signed-off-by: Sarthak Garg >> --- >> drivers/mmc/host/sdhci-msm.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c >> index 4e5edbf2fc9b..eca6a09a4547 100644 >> --- a/drivers/mmc/host/sdhci-msm.c >> +++ b/drivers/mmc/host/sdhci-msm.c >> @@ -355,7 +355,8 @@ static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host) >> */ >> if (ios.timing == MMC_TIMING_UHS_DDR50 || >> ios.timing == MMC_TIMING_MMC_DDR52 || >> - ios.timing == MMC_TIMING_MMC_HS400 || >> + (ios.timing == MMC_TIMING_MMC_HS400 && >> + ios.clock == MMC_HS200_MAX_DTR) || > It's a bit ugly that sdhci_msm_execute_tuning() passes ios.clock as an > argument to msm_set_clock_rate_for_bus_mode(), which then calls > msm_get_clock_mult_for_bus_mode() where you reach back into ios.clock. > > In fact, having msm_get_clock_mult_for_bus_mode() reach into > host->mmc->ios to get ios.timing, seems a violation of the original > intent of the prototype. > > > How about cleaning this up and passing "timing" as an argument to > msm_set_clock_rate_for_bus_mode(), and then pass host, clock, and timing > to msm_get_clock_mult_for_bus_mode()? > > That way we avoid this mix of passing parameters to the functions in > both arguments and in state at the same time. > > Regards, > Bjorn Sure will update in V2. Regards, Sarthak >> host->flags & SDHCI_HS400_TUNING) >> return 2; >> return 1; >> -- >> 2.34.1 >> >>