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Mon, 02 Mar 2026 21:29:13 -0800 (PST) X-Received: by 2002:a17:90b:51cd:b0:356:1f96:9fdd with SMTP id 98e67ed59e1d1-35965ce17f9mr14084387a91.33.1772515753194; Mon, 02 Mar 2026 21:29:13 -0800 (PST) Received: from [10.218.28.224] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3599c4c0f80sm1103599a91.16.2026.03.02.21.29.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Mar 2026 21:29:12 -0800 (PST) Message-ID: <5de8797f-a131-4ad5-97e8-005b751bdad5@oss.qualcomm.com> Date: Tue, 3 Mar 2026 10:59:06 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes To: Konrad Dybcio , Akhil P Oommen Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio References: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> <20260220-gpucc_sm8750_v2-v3-3-6c5408564c3c@oss.qualcomm.com> <7dbc0e99-cffb-403a-be7a-27d1b47712fd@oss.qualcomm.com> <8d658491-bc1c-410a-97f5-bde1a00764b2@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <8d658491-bc1c-410a-97f5-bde1a00764b2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Pv2ergM3 c=1 sm=1 tr=0 ts=69a671aa cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=e-IyLFVPmCgX-Kw4_c0A:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: r5V9D9x-ckDcHjq6VuxaB1qBbaSy4vJJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDAzMyBTYWx0ZWRfXxKE2JAdSwE3R gP4pnjrcxTSFA2SlM7oN0LX//GlcYXVb+NgomyhlUdTpCUbmT12CYMlpd3SeHLHLmKS8/NAG6rg L7j6VgEgd5Th96tRMHamoOkTsmEKRa1A3+we4ixbwWriIf/pYucjieWJrlFUqj0QI52p4+oV27T wp/X7XWg7KQ+Xx+TawzUEuUr/JJswSkD7+ZKGgqExkXQkW2DCoUMMi2n2FQh+L7jiiZcWNwbCe7 FoNGMcsZTMQ+aTJXPpftBoMeqHioPWIyYv8fxB2HXi3yE7KKMmAmL/nz7XzC6VD/xyPi5OjK/2z CYRrzo9u9c5FuTPQMwnDxFZGXethFxDiqhxSHglxmccwcjirmV9Aqb4viRb4Fw+kIcX9WjASoGL iSQYaeYcZEJ8BVaDRHZOwAtcBv5+RrQ2Oo9/92PGaRRSRYP/t3MfL425UNSsd4umF2kT0Ot4auM 1iPXFGgw0atJGvQ1Rwg== X-Proofpoint-GUID: r5V9D9x-ckDcHjq6VuxaB1qBbaSy4vJJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_05,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030033 On 2/23/2026 6:51 PM, Konrad Dybcio wrote: > On 2/21/26 7:22 PM, Akhil P Oommen wrote: >> On 2/20/2026 11:24 AM, Taniya Das wrote: >>> From: Konrad Dybcio >>> >>> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this >>> is simply a separate block housing the GX GDSC) nodes, required to >>> power up the graphics-related hardware. >>> >>> Make use of it by enabling the associated IOMMU as well. The GPU itself >>> needs some more work and will be enabled later. >>> >>> Signed-off-by: Konrad Dybcio >>> Co-developed-by: Taniya Das >>> Signed-off-by: Taniya Das >>> --- >>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 64 ++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 64 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >>> index f56b1f889b857a28859910f5c4465c8ce3473b00..0cc931d0bc96e9563ce4e7989ecd4ba50bd424f8 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >>> @@ -4,7 +4,9 @@ >>> */ >>> >>> #include >>> +#include >>> #include >>> +#include >>> #include >>> #include >>> #include >>> @@ -3001,6 +3003,30 @@ videocc: clock-controller@aaf0000 { >>> #power-domain-cells = <1>; >>> }; >>> >>> + gxclkctl: clock-controller@3d64000 { >>> + compatible = "qcom,sm8750-gxclkctl"; >>> + reg = <0x0 0x03d64000 0x0 0x6000>; >>> + >>> + power-domains = <&rpmhpd RPMHPD_GFX>, >>> + <&rpmhpd RPMHPD_GMXC>, >>> + <&gpucc GPU_CC_CX_GDSC>; >>> + >>> + #power-domain-cells = <1>; >>> + }; >>> + >>> + gpucc: clock-controller@3d90000 { >>> + compatible = "qcom,sm8750-gpucc"; >>> + reg = <0x0 0x03d90000 0x0 0x9800>; >>> + >>> + clocks = <&bi_tcxo_div2>, >>> + <&gcc GCC_GPU_GPLL0_CLK_SRC>, >>> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >>> + >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + #power-domain-cells = <1>; >> >> On Pakala and newer GPUs, we need to scale GMU (which is connected to >> the CX GDSC) freq. Is this DT description sufficient to allow scaling of >> GMU OPP? > > No, certainly not. > > I see that GPU_CC on this one is exclusively powered by VDD_CX, with > some MXA backing, so the natural course of action would be to add a > RPMHPD_CX power-domains handle here. Then, voting on the CX_GDSC will > propagate the performance state to RPMHPD_CX. > > Taniya, I see there's also some MXA backing. Do we need to scale it, > or is "just ON" fine here? > MXA is required along with CX and I will update the bindings accordingly to take care of required power domains. -- Thanks, Taniya Das