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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-246688645eesm94817945ad.99.2025.08.26.05.11.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Aug 2025 05:11:47 -0700 (PDT) Message-ID: <5df27be9-0347-49d1-ba1e-21d6a2172314@oss.qualcomm.com> Date: Tue, 26 Aug 2025 20:11:41 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/3] coresight: tpda: add sysfs node to flush specific port To: James Clark , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Tingwei Zhang References: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> <20250826070150.5603-4-jie.gan@oss.qualcomm.com> <3ac2954e-5663-4ea0-bc1d-a09e1992af5b@linaro.org> <939eb45c-f48e-40ce-86e8-710afa2b5c9b@linaro.org> Content-Language: en-US From: Jie Gan In-Reply-To: <939eb45c-f48e-40ce-86e8-710afa2b5c9b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX1+TWZ5uY+hqJ 54WoTk/aazPV0V89EYWyhIWrmtgc6U4vgw56AUZv9lTFQ/GT+BiMN+GQwjxs6NGB1it6MrVJrmy ex60ePlRL+B9ySw0vGSbueUZqOY53GlBV3OS7tcB7RGJz8EaGnltZdt7RM2AgkTCdLnkRDeuZxS CMs7EoT8R4sQyEC9t+AM3oosLC/hrKWLhXG1+ewVcw8LXlhYNj2HJ/LpNVjGYN3dInFqFoERBU2 dhfruNIJ2xZr7ZLcSHCw2iD+dMMC3tSOPXVHebjcJnZflK46YPcm70TnRsNW3GoifWlQsXao1QW R4K7wtWsD8NBdM8j32g7zdVtTMZ/w3z4fM7RdFGqrjkIRvY/TofBnCQ84ONmvO4drIkWJwGLaVX dg7kyQm5 X-Authority-Analysis: v=2.4 cv=Lco86ifi c=1 sm=1 tr=0 ts=68ada485 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=-hWpzLsPYw3_ZpqOosEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: pBzlla03RsmCJjG6lOWCuaDW75dNzsBc X-Proofpoint-ORIG-GUID: pBzlla03RsmCJjG6lOWCuaDW75dNzsBc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 clxscore=1015 malwarescore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 On 8/26/2025 5:54 PM, James Clark wrote: > > > On 26/08/2025 10:39 am, Jie Gan wrote: >> >> >> On 8/26/2025 5:27 PM, James Clark wrote: >>> >>> >>> On 26/08/2025 8:01 am, Jie Gan wrote: >>>> From: Tao Zhang >>>> >>>> Setting bit i in the TPDA_FLUSH_CR register initiates a flush request >>>> for port i, forcing the data to synchronize and be transmitted to the >>>> sink device. >>>> >>>> Signed-off-by: Tao Zhang >>>> Co-developed-by: Jie Gan >>>> Signed-off-by: Jie Gan >>>> --- >>>>   .../testing/sysfs-bus-coresight-devices-tpda  |  7 +++ >>>>   drivers/hwtracing/coresight/coresight-tpda.c  | 45 +++++++++++++++ >>>> ++++ >>>>   drivers/hwtracing/coresight/coresight-tpda.h  |  1 + >>>>   3 files changed, 53 insertions(+) >>>> >>>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >>>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>>> index e827396a0fa1..8803158ba42f 100644 >>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>>> @@ -41,3 +41,10 @@ Contact:    Jinlong Mao >>>> , Tao Zhang >>>   Description: >>>>           (RW) Configure the CMB/MCMB channel mode for all enabled >>>> ports. >>>>           Value 0 means raw channel mapping mode. Value 1 means >>>> channel pair marking mode. >>>> + >>>> +What:        /sys/bus/coresight/devices//port_flush_req >>>> +Date:        August 2025 >>>> +KernelVersion:    6.17 >>>> +Contact:    Jinlong Mao , Tao Zhang >>>> , Jie Gan >>>> +Description: >>>> +        (RW) Configure the bit i to requests a flush operation of >>>> port i on the TPDA. >>>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >>>> hwtracing/coresight/coresight-tpda.c >>>> index 9e623732d1e7..c5f169facc51 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-tpda.c >>>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >>>> @@ -509,6 +509,50 @@ static ssize_t cmbchan_mode_store(struct device >>>> *dev, >>>>   } >>>>   static DEVICE_ATTR_RW(cmbchan_mode); >>>> +static ssize_t port_flush_req_show(struct device *dev, >>>> +                   struct device_attribute *attr, >>>> +                   char *buf) >>>> +{ >>>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>> +    unsigned long val; >>>> + >>>> +    guard(spinlock)(&drvdata->spinlock); >>>> +    if (!drvdata->csdev->refcnt) >>>> +        return -EPERM; >>>> + >>>> +    val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); >>>> +    return sysfs_emit(buf, "%lx\n", val); >>> >>> Decimal would be better for a port number that goes from 0 - 127. If >>> you really want to use hex then don't you need to prefix it with 0x? >>> Otherwise you can't tell the difference between decimal 10 and hex >>> 10, and it's not documented that it's hex either. >>> >> >> Got it. I will fix the code here, and update the description in document. >> >>>> +} >>>> + >>>> +static ssize_t port_flush_req_store(struct device *dev, >>>> +                    struct device_attribute *attr, >>>> +                    const char *buf, >>>> +                    size_t size) >>>> +{ >>>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>> +    unsigned long val; >>>> + >>>> +    if (kstrtoul(buf, 0, &val)) >>>> +        return -EINVAL; >>>> + >>>> +    /* The valid value ranges from 0 to 127 */ >>>> +    if (val > 127) >>>> +        return -EINVAL; >>>> + >>>> +    guard(spinlock)(&drvdata->spinlock); >>>> +    if (!drvdata->csdev->refcnt) >>>> +        return -EPERM; >>>> + >>>> +    if (val) { >>> >>> If 0 - 127 are valid don't you want to write 0 too? >> >> It's 1-127 here. 0 may leads to an unexpected issue here. >> >> Thanks, >> Jie >> > > Then can't the above be this: > >   /* The valid value ranges from 1 to 127 */ >   if (val < 1 || val > 127) >     return -EINVAL; > > But I'm wondering how you flush port 0? > BIT(0) represents port 0 with value 1 and the default value 0 means nothing will be triggered here. > Isn't the default value 0? So if you never write to port_flush_req then > you'd flush port 0, but why can't you change it back to 0 after writing > a different value? We can change the value back to 0 but I think we shouldn't do this although I haven't suffer issue after I changed it back to 0(for bit). Because the document mentioned: "Once set, the bit remains set until the flush operation on port i completes and the bit then clears to 0". So I think we should let the flush operation finish as expected and clear the bit by itself? Or may suffer unexpected error when try to interrupt the flush operation? Thanks, Jie >>> >>>> +        CS_UNLOCK(drvdata->base); >>>> +        writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); >>>> +        CS_LOCK(drvdata->base); >>>> +    } >>>> + >>>> +    return size; >>>> +} >>>> +static DEVICE_ATTR_RW(port_flush_req); >>>> + >>>>   static struct attribute *tpda_attrs[] = { >>>>       &dev_attr_trig_async_enable.attr, >>>>       &dev_attr_trig_flag_ts_enable.attr, >>>> @@ -516,6 +560,7 @@ static struct attribute *tpda_attrs[] = { >>>>       &dev_attr_freq_ts_enable.attr, >>>>       &dev_attr_global_flush_req.attr, >>>>       &dev_attr_cmbchan_mode.attr, >>>> +    &dev_attr_port_flush_req.attr, >>>>       NULL, >>>>   }; >>>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >>>> hwtracing/coresight/coresight-tpda.h >>>> index 00d146960d81..55a18d718357 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-tpda.h >>>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >>>> @@ -10,6 +10,7 @@ >>>>   #define TPDA_Pn_CR(n)        (0x004 + (n * 4)) >>>>   #define TPDA_FPID_CR        (0x084) >>>>   #define TPDA_SYNCR        (0x08C) >>>> +#define TPDA_FLUSH_CR        (0x090) >>>>   /* Cross trigger FREQ packets timestamp bit */ >>>>   #define TPDA_CR_FREQTS        BIT(2) >>> >>> >> > >