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Thu, 22 Oct 2026 05:22:23 -0700 (PDT) Received: from [10.217.219.98] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ea3b412756sm23642595ad.24.2026.10.22.05.22.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Oct 2026 05:22:22 -0700 (PDT) Message-ID: <5dfd7245-c2c0-4468-95ed-6bb8a385da98@oss.qualcomm.com> Date: Thu, 22 Oct 2026 17:52:15 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/8] soc: qcom: geni-se: Populate clk_perf_tbl with SE source clock frequencies from perf OPP table To: Praveen Talari , konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20261015-derive_clk_perf_tbl_from_perf_domain_opp_table-v3-0-5da1096243c9@oss.qualcomm.com> <20261015-derive_clk_perf_tbl_from_perf_domain_opp_table-v3-1-5da1096243c9@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20261015-derive_clk_perf_tbl_from_perf_domain_opp_table-v3-1-5da1096243c9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: DGx13CFiEcY1W9kIuYKQMshWpxTcPX9s X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDA0OSBTYWx0ZWRfX7NeYHYAYRTnf 7hZ0w4dMTd9tBFtxQoj3Sw1yS8zIoXLiTuewyY5DYWzzK/hc4OmIeAuPHbrLHYdrBREqvSOlUtr c5oH79yx4aWDMdUUhR2NJPYVIExdwPc= X-Proofpoint-ORIG-GUID: DGx13CFiEcY1W9kIuYKQMshWpxTcPX9s X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDA0OSBTYWx0ZWRfX+8tI2TvnWlXW PUGCdY8YQ1IvpNjo63zTdRx4uenYNvMHq17T+2TwQuZNLO4vqMWAUUIJTYPt5iA5RrvHS3ewOPR KHsGj1S4Mkk4CvAgBfzXoIuEKk1tObO9Gzaa+eg+yY1S6L5KLzrKbQ9EpqkSwaWp7DBkD/E8kOa UGM9KGJDb3vMD4qwpd1QE0q+9NqnwionjtwGL36JkjQCew1e020uHDztaIGjGSZRYwqroN7okt5 ZMQpDdhKx2JA0MHb+30dJf3UtZ01uTXP1nKSb0wWvWZvjuagcqjfqc2ui27TMn2OBmvbhIEGwYD DYo3bV7pOrn8xT2S5P451ZUO1QZObIDdge7jfUKdmg/6LE24Ch0H9n5A7HwAixEeM3IQBigYI50 jhutibOzFTO6XD3wc3E3lk+FDg21q+sHW1Oa0Xf6pAg2lr0lcBFFGer7Wwvam3mv/tYQRMoqX6Z U+bvFxVHIlnYsxPOvHw== X-Authority-Analysis: v=2.4 cv=dOszC+Zb c=1 sm=1 tr=0 ts=6ada0000 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=ddSnBWzqd8mu_d83chYA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-22_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 phishscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220049 On 10/15/2026 6:28 PM, Praveen Talari wrote: > Currently, on the SA8255P platform, protocol drivers attached via > geni_se_domain_attach() treat each OPP on the perf domain as directly > corresponding to a protocol value such as a baudrate or requested > frequency, and simply request that OPP via > geni_se_set_perf_level()/geni_se_set_perf_opp(). This does not allow > computing a source clock and divider combination for a protocol > requested frequency, unlike the Linux clock managed path which derives > this from se->clk_perf_tbl via geni_se_clk_freq_match(), and then > applies the matched source clock frequency with dev_pm_opp_set_rate(). > > Change this by treating the OPP table exposed on the perf domain > device as representing the actual SE HW supported source clock > frequencies, the same role clk_perf_tbl plays for the Linux clock > managed path. Populate se->clk_perf_tbl and se->num_clk_levels by > iterating over this OPP table in geni_se_domain_attach(), so that > protocol drivers on the firmware managed (SA8255P) path can also use > geni_se_clk_freq_match() to pick the closest supported source clock > frequency and calculate the required divider, and apply it with > dev_pm_opp_set_rate() the same way as it is done for the Linux clock > managed path, instead of relying on a direct frequency/baudrate-to- > perf-level mapping. > > Signed-off-by: Praveen Talari > --- Reviewed-by: Mukesh Kumar Savaliya