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Wed, 28 Oct 2026 08:06:27 -0700 (PDT) Received: from [192.168.1.31] ([85.196.172.179]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd4ea0ccsm626317566b.16.2026.10.28.08.06.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Oct 2026 08:06:26 -0700 (PDT) Message-ID: <5e30518c-c6d3-458f-a0ba-f202f5b428e4@oss.qualcomm.com> Date: Wed, 28 Oct 2026 17:06:24 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] media: qcom: camss: clamp VFE clock rates to the highest level From: "Gjorgji Rosikopulos (Consultant)" To: Atanas Filipov , Loic Poulain Cc: Bryan O'Donoghue , Mauro Carvalho Chehab , Vladimir Zapolskiy , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261023152857.2859767-1-atanas.filipov@oss.qualcomm.com> <20261023152857.2859767-2-atanas.filipov@oss.qualcomm.com> <07f884f2-bf92-4264-a289-d40fda9508e3@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <07f884f2-bf92-4264-a289-d40fda9508e3@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 8gvnSeQvIEXmbGh5SkiUHn3rZHyG0Cq5 X-Authority-Analysis: v=2.4 cv=DtDDa2/+ c=1 sm=1 tr=0 ts=6ae20f75 cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=Q/e3f29T3Hw2hnAEzBPF7w==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=D-oFrpvt22n0kU7c7gUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI4MDA2MCBTYWx0ZWRfX3iR4vnoUPin+ t9en18vGPcDyaqzpqs03Q3emQy4Vu7KNr6S1sMQsI0YVJ7kBG4JmsvWGjRO4wHAhdQNnEvnTaPh diwpbe8XKCs1SyfIUrzaoac2PtRSR24drBkCyjuHeVGY70wtekDPzHjyJcbhfJPaO3+DqZuyDVM Kt71By9lqjo8RQ4ZxwYrZcC1JqIJGGpr9ZQJPjtZOrF5UdC4ZCc/fFXT7uuWV0oxyJppyYfXALa +eS1y100Nlpyiji+EqFDExq2LDP91IwE3HaQU3qQCehBM5b59bqsi4YZOFx552cRkaqNNd/Nb0j pTNg+XD5+0dHf9+zI3WOqYq9+9JrcmqINtqJ8B++brkMo6KeeQ3qsU/oBunJrsVji1ok+ECCFmL D6b4ZnKC1p/490eVW7EZSlY/6pI30NxouHjM8OrU1ARZx/rKjVJXVD0V+ww1FYdmvGXIpWMINz5 aXlbBExIweMCqQBCe1g== X-Proofpoint-GUID: 8gvnSeQvIEXmbGh5SkiUHn3rZHyG0Cq5 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI4MDA2MCBTYWx0ZWRfX+oq5Pge5qoyf hRfc3jtlJdKYeTOnTROODItFtR+BtqLdnBAyET0DFtCumREDL/PLJZsfWEpumBb2krd6PJkGOBZ p+WL2hGy0cLg83kxzsvL0eiPl6av4CE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-28_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 phishscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610280060 On 10/23/2026 10:07 PM, Gjorgji Rosikopulos (Consultant) wrote: > Hi Atanas, Loic, All, > > On 10/23/2026 6:50 PM, Atanas Filipov wrote: >> On 10/23/2026 6:45 PM, Loic Poulain wrote: >>> On Fri, Oct 23, 2026 at 5:29 PM Atanas Filipov >>> wrote: >>>> >>>> The VFE fails to power on when the pixel rate exceeds the highest rate >>>> listed for any of its clocks. The rate tables of the VFE clocks are >>>> independent and need not have the same number of levels, so a clock >>>> with a lower top rate than the VFE core clock, such as the SC7280 >>>> camnoc_axi clock, makes the VFE reject pixel rates the core clock >>>> still supports. >>>> >>>> Clamp each clock to its highest listed rate instead, and warn that the >>>> pixel rate exceeds it when the clock lists more than one rate. Take the >>>> clamp into account when another line powers on an already running VFE, >>>> so that a clock running at its highest rate does not reject the >>>> request. >>> >>> IMO, this function has become a bit messy. We should split the core >>> clock selection into a dedicated helper, as it is directly tied to the >>> pixel rate. The AXI clock scaling/selection should be handled >>> separately, potentially through the interconnect (ICC) framework (when >>> available). >>> >>> Regards, >>> Loic >>> >> >> I completely agree. I just don't want to mix the two issues, as >> requested by the reviewers. IMO, if we can reach an agreement on the ICC >> migration, that would be great. >> >> Regards, >> Atanas >> > > There have been several discussions about this topic. > I would like to summarize the background here and reopen the discussion > about the direction proposed by Atanas. > > The issue initially came up with the JPEG encoder driver, which is > represented as a separate device. Dmitry identified that changing the > camnoc_ax clock from the JPEG driver conflicts with CAMSS. > I will not revisit the discussion about why JPEG is not part of CAMSS, > as this has already been discussed extensively. > > Currently, CAMSS is represented as a single device and drives the front-end > blocks that write data to memory, such as VFE, IFE, and TFE. > > Depending on the hardware architecture, CAMSS may contain different number > of front-end blocks. Some camera subsystems also contain offline engines > like JPEG and OPE. > All these engines write data to memory through the internal CAMNOC and > share the camnoc_axi clock. > > The relevant topology can be summarized as follows: > > CAMSS device: Front end -> CAMNOC -> MNOC > OPE device: OPE -> CAMNOC -> MNOC > JPEG device: JPEG -> CAMNOC -> MNOC > > An ICC path is already available for MNOC, and each device can vote on it. > > CAMSS currently has two issues on this topic that need to be addressed. > > 1. Clock aggregation for concurrent streaming, As described in the cover > letter, CAMSS currently does not aggregate the clock requirements when > multiple front-end engines are streaming concurrently. > > 2. ICC bandwidth voting > The currently available MNOC ICC voting is implemented using max bandwidth > values. This can increase power consumption in single-camera use cases. > This is not included in this patchset. > > Addressing the first issue depends, to some extent, on the direction we > choose for CAMNOC ICC support. Atanas has proposed two possible approaches. > > 1. [PATCH v2 0/3] Add Qualcomm CAMNOC ICC provider > > The patchset adds an initial CAMNOC ICC provider with multiple ports, where > each port represents an engine client of the CAMNOC. > > This allows a device such as CAMSS, which is represented as a single device, > to vote independently through different CAMNOC ports. The CAMNOC ICC provider > can then aggregate the votes and calculate the appropriate camnoc_axi clock > rate. > > 1. [PATCH v3 0/3] Use icc-clk for the SM8250 camera NoC AXI clock > > The ICC framework, together with CAMCC support, can represent a clock as an > ICC provider. The implementation is relatively simple because it reuses the > existing infrastructure, the camnoc_axi clock only needs to be exposed as an > ICC provider. > > The limitation of this approach is that a device such as CAMSS cannot vote for > each engine independently. After carefully reviewing the ICC code and discussing it with Georgi Dzakov, I believe this assumption is incorrect. ICC aggregation is performed per client, so each VFE sub-device can call icc_get() for the same endpoint and achieve the desired aggregate bandwidth. So i think is better to continue with this approach and see how the things will look like with camss and jpeg migrated to this provider. ~Gjorgji