From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m49230.qiye.163.com (mail-m49230.qiye.163.com [45.254.49.230]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B24A212550; Wed, 9 Sep 2026 01:12:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.230 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788916356; cv=none; b=nAsvgVyE52UrZUvRSoSmyGjIhOuFRfB636fKXpy8okwr7ivjVkHkp2w1pua1Tun0YWwO+YY2kLB/d1g5bBiNZ0H3T29yEUjoAecLilBX4SG4CS4RnO6YWSZm3YAkeV4/Hzh41dapLobucZJEtKb8dICG4xS296G//ICVCx6M7bo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788916356; c=relaxed/simple; bh=AmXAISq+H+bqIf5oxGF6dj30yrX2tlJUIyGrO1l0Nbg=; h=Message-ID:Date:MIME-Version:Cc:Subject:To:References:From: In-Reply-To:Content-Type; b=B7wsuHmDJbLj0G+YXT98KAyu7/CGdoWw+/fCD/lhYExi0TeUqgPH5JLc+lTc9YQF/75TUvY+97NY9VFZxEO/QXyiGlk1+b5hcJPgW/Ou1+IIhCTKXev3vXA2zmLNsVsV6Xk1Q+ZfyKONyKPMskKEf5NVqSzEygFw5J2RcZB6n6w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=BPSKVn6h; arc=none smtp.client-ip=45.254.49.230 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="BPSKVn6h" Received: from [172.16.12.48] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4d098a741; Wed, 9 Sep 2026 09:07:11 +0800 (GMT+08:00) Message-ID: <5e4f9b07-f11b-4d52-b1d4-3b680b457eb3@rock-chips.com> Date: Wed, 9 Sep 2026 09:07:10 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCH v6 07/10] PCI: dw-rockchip: Add pme_turn_off support To: Sebastian Reichel , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> <20260908-rockchip-pcie-system-suspend-v6-7-fbabcca9921b@collabora.com> From: Shawn Lin In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-7-fbabcca9921b@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0aa083b45eab03a4kunma4967f8f441eaa X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZQh9LSVZJTE5LHxgaTk 5DQkxWFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSU9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=BPSKVn6h6LN29eN2GrvbN/1+zF4JRqE/CggubnWskTRYkjICKOsaiYGhd489E3P5YTXfIGIdIFXhk0ak0Pzfs+tVgHPiVJVCqwo6hIP5KE7e/rA4Cj5arkRjcoz4e+MM0s1H1MwPxVBp9b3zolVMrF7Q/27lgrCu4HTuAS1rFjI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=8O3sEMbdttlkjB7YR4EWG8ZoEn7yeFuuCH+g88V++TQ=; h=date:mime-version:subject:message-id:from; 在 2026/09/08 星期二 22:51, Sebastian Reichel 写道: > Prepare Rockchip PCIe controller for system suspend support by > adding the PME turn off operation. > Reviewed-by: Shawn Lin > Signed-off-by: Sebastian Reichel > --- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 44 +++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index 1e48099e36e4..17530507e41b 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -45,6 +45,7 @@ > #define PCIE_CLIENT_LD_RQ_RST_GRT FIELD_PREP_WM16(BIT(3), 1) > #define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1) > #define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0) > +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 > > /* Interrupt Status Register Related to Legacy Interrupt */ > #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 > @@ -64,6 +65,11 @@ > > /* Interrupt Mask Register Related to Miscellaneous Operation */ > #define PCIE_CLIENT_INTR_MASK_MISC 0x24 > +#define PCIE_CLIENT_POWER 0x2c > +#define PCIE_CLIENT_MSG_GEN 0x34 > +#define PME_READY_ENTER_L23 BIT(3) > +#define PME_TURN_OFF FIELD_PREP_WM16(BIT(4), 1) > +#define PME_TO_ACK FIELD_PREP_WM16(BIT(9), 1) > > /* Power Management Control Register */ > #define PCIE_CLIENT_POWER_CON 0x2c > @@ -452,8 +458,46 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) > return 0; > } > > +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); > + struct device *dev = rockchip->pci.dev; > + u32 status; > + int ret; > + > + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ > + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, > + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) { > + dev_warn(dev, "Failed to send PME_Turn_Off\n"); > + return; > + } > + > + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */ > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX, > + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) { > + dev_warn(dev, "Failed to receive PME_TO_Ack\n"); > + return; > + } > + > + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ > + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX); > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER, > + status, status & PME_READY_ENTER_L23, > + PCIE_PME_TO_L2_TIMEOUT_US / 10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) > + dev_err(dev, "Failed to get ready to enter L23 message\n"); > +} > + > static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { > .init = rockchip_pcie_host_init, > + .pme_turn_off = rockchip_pcie_pme_turn_off, > }; > > /* >