From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AAD4175A89 for ; Sun, 28 Jun 2026 17:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782669321; cv=none; b=A4ikoS/+QItaeYcWY2xK3Yrwt7jd3EQ7+rR7mbXgFtbrrp41uLDnBWasm0cqgmNSNmcslWUy/pw3sPsZTAe0NWzwKFa6bWVZZ97ETGCu7chP6jYd/HkRCjuL2epi3wOn4izAJGDgBN/yXmL2WqaYPK55zNVtWXhgIhnbqQRAFkg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782669321; c=relaxed/simple; bh=2CITBd7/18CBzbO8NNksy39726jDFXG6TU9lyUfD+GA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=cqY0c/EF32ulkB4+cAV5tJ/OioWUqmTFa7cr1NuekQCsSA6by4OCv8YI5KQNYYMDYXr/btYbtzPfLT7HTygp+yizsWFOZ7GS8SqQptzHcFFckEJOZsvfTl5LRGMdYTCU+fett2j/HsN2FT1wqazOj2lI1BKVcWzMAX+T5o2LSRA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=q6N3im/n; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="q6N3im/n" Message-ID: <5e59c3a3-b492-40f0-9db1-5ef9f95d77b6@packett.cool> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1782669317; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U0xAeg+eNrWlm0+W61UvKbaI5qPbR3lC4Fub+e8id8w=; b=q6N3im/n2Y0zVf+KlcOnIUa0QJI6dOf5WbsOmsHDcV1V5r+az6+w2ARCmwN42KuP19FePn ChaE6AkkYL3LvVuKa/LmB6yKZn38NvDYTciUzlZuKgO0WEWqPNLwzHo0Mmjaurs6MAjPlL AJH3i4C8l61sx+mGAkemkR1HhW2Am9iVHpCkMZ34ea6N41fhJiHK2pfFrbsj4VyKEdt11d ksEALkH/LgFgz/oYJuEL+inrpbXzlzy44ZdUuc8APNTkwGYLSUeGiZDFQ7fhnNSKtZCdNj 5XmMcfUQlOdIJwS7AbcgKSeEBvxRn5gnMrVTqQjazRQnW5eJp4HhQg76emEwpQ== Date: Sun, 28 Jun 2026 14:54:52 -0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v3 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper To: Maulik Shah , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad References: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com> <20260616-hamoa_pdc_v3-v3-3-4d8e1504ea75@oss.qualcomm.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Val Packett In-Reply-To: <20260616-hamoa_pdc_v3-v3-3-4d8e1504ea75@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT On 6/16/26 6:25 AM, Maulik Shah wrote: > pdc->enable_intr() function already points to respective version > specific enable function. pdc_enable_intr() now only kept as wrapper. > Remove the wrapper and invoke pdc->enable_intr() from caller. > > Locking in pdc_enable_intr() applies lock to all pdc->enable_intr() > however its only required for pdc_enable_intr_bank() which uses > a shared bank across all interrupts. pdc_enable_intr_cfg() do not > required locking as IRQ_CFG registers are one per interrupt. Move > locking accordingly. > > Signed-off-by: Maulik Shah > --- > drivers/irqchip/qcom-pdc.c | 13 ++++--------- > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c > index b9acb0f25c9c..6c556464d37c 100644 > --- a/drivers/irqchip/qcom-pdc.c > +++ b/drivers/irqchip/qcom-pdc.c > @@ -206,6 +206,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on) > index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); > mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); > > + guard(raw_spinlock)(&pdc->lock); > [..] whoops.. [    0.197090] BUG: spinlock bad magic on CPU#7, swapper/0/1 [    0.197104]  lock: 0xffff0001022e37b0, .magic: 00000000, .owner: /-1, .owner_cpu: 0 [    0.197122] CPU: 7 UID: 0 PID: 1 Comm: swapper/0 Not tainted 7.1.0-next-20260626-uwu+ #128 PREEMPT(full) [    0.197129] Hardware name: motorola Motorola Edge 30 (Tianma)/Motorola Edge 30 (Tianma), BIOS 2026.07-rc2-g432bcf301c03-dirty 07/01/2026 [    0.197133] Call trace: [    0.197135]  show_stack+0x24/0x38 (C) [    0.197148]  __dump_stack+0x28/0x38 [    0.197156]  dump_stack_lvl+0x7c/0xa8 [    0.197165]  dump_stack+0x18/0x30 [    0.197172]  spin_dump+0x7c/0x98 [    0.197179]  do_raw_spin_lock+0xa4/0x140 [    0.197189]  _raw_spin_lock+0x2c/0x40 [    0.197195]  pdc_enable_intr_bank+0x40/0x128 [    0.197201]  qcom_pdc_probe+0x3bc/0x520 Gotta also move the spinlock init to before the call to pdc_setup_pin_mapping.. ~val