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([2a02:810d:15c0:828:687d:8c5:41cb:9883]) by smtp.gmail.com with ESMTPSA id t18-20020a17090616d200b0094f969e877bsm2242742ejd.43.2023.04.21.09.43.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Apr 2023 09:43:48 -0700 (PDT) Message-ID: <5e622e88-5287-1ffc-aa9b-c7c85a661fd9@linaro.org> Date: Fri, 21 Apr 2023 18:43:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v2 7/7] ASoC: dt-bindings: mediatek,mt8188-afe: add audio properties Content-Language: en-US To: Trevor Wu , broonie@kernel.org, lgirdwood@gmail.com, tiwai@suse.com, perex@perex.cz, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: alsa-devel@alsa-project.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230421100905.28045-1-trevor.wu@mediatek.com> <20230421100905.28045-8-trevor.wu@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20230421100905.28045-8-trevor.wu@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/04/2023 12:09, Trevor Wu wrote: > Assign top_a1sys_hp clock to 26M, and add apll1_d4 to clocks for switching > the parent of top_a1sys_hp dynamically > On the other hand, "mediatek,infracfg" is included for bus protection. > > Signed-off-by: Trevor Wu > --- > .../bindings/sound/mediatek,mt8188-afe.yaml | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml > index 82ccb32f08f2..812e0702ca36 100644 > --- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml > +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml > @@ -29,6 +29,10 @@ properties: > $ref: /schemas/types.yaml#/definitions/phandle > description: The phandle of the mediatek topckgen controller > > + mediatek,infracfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: The phandle of the mediatek infracfg controller > + > power-domains: > maxItems: 1 > > @@ -52,6 +56,7 @@ properties: > - description: mux for i2si1_mck > - description: mux for i2si2_mck > - description: audio 26m clock > + - description: audio pll1 divide 4 > > clock-names: > items: > @@ -73,6 +78,7 @@ properties: > - const: i2si1_m_sel > - const: i2si2_m_sel > - const: adsp_audio_26m > + - const: apll1_d4 > > mediatek,etdm-in1-cowork-source: > $ref: /schemas/types.yaml#/definitions/uint32 > @@ -147,6 +153,8 @@ required: > - power-domains > - clocks > - clock-names > + - assigned-clocks > + - assigned-clock-parents You were explaining it last time, but it did not solve my concerns. Requiring these properties means that your hardware boots with incorrect clock parents, including result of any firmware, and there is no way it can correctly work without reparenting. What's more, this means that your clock hierarchy does not include these clocks for some reason, e.g. you need to reparent parents of some parent of your clock input, otherwise device cannot work. Cannot work never ever. Is this the case? Have in mind that bindings are used also by other OS and projects, like bootloaders, firmware etc. Best regards, Krzysztof