From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
To: Zhengping Zhang <zhengping.zhang@airoha.com>,
linusw@kernel.org, lorenzo@kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
brgl@kernel.org, naseefkm@gmail.com, benjamin.larsson@genexis.eu,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
lei.dong@airoha.com, ansuelsmth@gmail.com
Subject: Re: [PATCH 04/12] pinctrl: airoha: an7581: fix PHY LED GPIO group assignments
Date: Sun, 15 Nov 2026 17:02:12 +0300 [thread overview]
Message-ID: <5e681d92-9772-42e3-aae8-47faacf6d850@iopsys.eu> (raw)
In-Reply-To: <20261110094339.749110-5-zhengping.zhang@airoha.com>
according to an7581 datasheet
* LED0 uses GPIO33-35 and GPIO42 * LED1 uses GPIO43-46 so patch is not
needed
On 11/10/26 12:43, Zhengping Zhang wrote:
> [You don't often get email from zhengping.zhang@airoha.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> The PHY LED function tables associate LED0 mux bits with the GPIO pads
> used by LED1, and vice versa. Selecting an LED function therefore
> programs the mux bit for a different pad from the requested group.
>
> The LED mux bits in SCU register 0x214 correspond to these GPIO pads:
>
> LAN0 LAN1 LAN2 LAN3
> LED0 mux bit 3 5 7 9
> LED0 GPIO 43 44 45 46
> LED1 mux bit 4 6 8 10
> LED1 GPIO 33 34 35 42
>
> Correct both the advertised groups and the function-group entries to
> match these assignments. This ensures that the pin claimed by pinctrl
> matches the pad controlled by the selected LED mux bit.
>
> Keep the existing mux masks and PHY source selections in the LED0/1
> mapping registers unchanged.
>
> Signed-off-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> ---
> drivers/pinctrl/airoha/pinctrl-an7581.c | 80 ++++++++++++-------------
> 1 file changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
> index bfb777594811b..3cbdfc31e97e5 100644
> --- a/drivers/pinctrl/airoha/pinctrl-an7581.c
> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
> @@ -594,28 +594,28 @@ static const char *const pwm_groups[] = {
> "gpio46", "gpio47", "gpio48", "gpio49"
> };
> static const char *const phy1_led0_groups[] = {
> - "gpio33", "gpio34", "gpio35", "gpio42"
> + "gpio43", "gpio44", "gpio45", "gpio46"
> };
> static const char *const phy2_led0_groups[] = {
> - "gpio33", "gpio34", "gpio35", "gpio42"
> + "gpio43", "gpio44", "gpio45", "gpio46"
> };
> static const char *const phy3_led0_groups[] = {
> - "gpio33", "gpio34", "gpio35", "gpio42"
> + "gpio43", "gpio44", "gpio45", "gpio46"
> };
> static const char *const phy4_led0_groups[] = {
> - "gpio33", "gpio34", "gpio35", "gpio42"
> + "gpio43", "gpio44", "gpio45", "gpio46"
> };
> static const char *const phy1_led1_groups[] = {
> - "gpio43", "gpio44", "gpio45", "gpio46"
> + "gpio33", "gpio34", "gpio35", "gpio42"
> };
> static const char *const phy2_led1_groups[] = {
> - "gpio43", "gpio44", "gpio45", "gpio46"
> + "gpio33", "gpio34", "gpio35", "gpio42"
> };
> static const char *const phy3_led1_groups[] = {
> - "gpio43", "gpio44", "gpio45", "gpio46"
> + "gpio33", "gpio34", "gpio35", "gpio42"
> };
> static const char *const phy4_led1_groups[] = {
> - "gpio43", "gpio44", "gpio45", "gpio46"
> + "gpio33", "gpio34", "gpio35", "gpio42"
> };
>
> static const struct airoha_pinctrl_func_group pon_func_group[] = {
> @@ -1067,90 +1067,90 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> };
>
> static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> };
>
> static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> };
>
> static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> };
>
> static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> };
>
> static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> };
>
> static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> };
>
> static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> };
>
> static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio33", GPIO_LAN0_LED1_MODE_MASK,
> LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio34", GPIO_LAN1_LED1_MODE_MASK,
> LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio35", GPIO_LAN2_LED1_MODE_MASK,
> LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> + AIROHA_PINCTRL_PHY_LED1("gpio42", GPIO_LAN3_LED1_MODE_MASK,
> LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> };
>
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-11-15 14:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 9:43 [PATCH 00/12] pinctrl: airoha: configure GPIO muxes explicitly and fix pad mappings Zhengping Zhang
2026-11-10 9:43 ` [PATCH 01/12] pinctrl: airoha: fix setting of GPIO direction Zhengping Zhang
2026-11-10 9:43 ` [PATCH 02/12] pinctrl: airoha: configure pin muxes on GPIO requests Zhengping Zhang
2026-11-10 9:43 ` [PATCH 03/12] dt-bindings: pinctrl: airoha: describe all EN7581 GPIO mux groups Zhengping Zhang
2026-11-15 14:00 ` Mikhail Kshevetskiy
2026-11-10 9:43 ` [PATCH 04/12] pinctrl: airoha: an7581: fix PHY LED GPIO group assignments Zhengping Zhang
2026-11-15 14:02 ` Mikhail Kshevetskiy [this message]
2026-11-10 9:43 ` [PATCH 05/12] pinctrl: airoha: an7581: select force GPIO mode on GPIO requests Zhengping Zhang
2026-11-15 14:21 ` Mikhail Kshevetskiy
2026-11-10 9:43 ` [PATCH 06/12] dt-bindings: pinctrl: airoha: describe all AN7583 GPIO mux groups Zhengping Zhang
2026-11-10 9:43 ` [PATCH 07/12] pinctrl: airoha: an7583: fix SPI pin mux config Zhengping Zhang
2026-11-10 9:43 ` [PATCH 08/12] pinctrl: airoha: an7583: fix eMMC " Zhengping Zhang
2026-11-10 9:43 ` [PATCH 09/12] pinctrl: airoha: an7583: use force GPIO mode for GPIO requests Zhengping Zhang
2026-11-15 14:23 ` Mikhail Kshevetskiy
2026-11-10 9:43 ` [PATCH 10/12] dt-bindings: pinctrl: airoha: describe all EN7523 GPIO mux groups Zhengping Zhang
2026-11-10 9:43 ` [PATCH 11/12] pinctrl: airoha: en7523: use force GPIO mode for GPIO requests Zhengping Zhang
2026-11-15 14:24 ` Mikhail Kshevetskiy
2026-11-10 9:43 ` [PATCH 12/12] MAINTAINERS: add myself as Airoha pinctrl co-maintainer Zhengping Zhang
2026-11-15 14:09 ` [PATCH 00/12] pinctrl: airoha: configure GPIO muxes explicitly and fix pad mappings Mikhail Kshevetskiy
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