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Mon, 16 Dec 2024 14:00:02 -0800 (PST) Message-ID: <5e878b5b-b49d-4757-8f7e-4b323a4998b3@sifive.com> Date: Mon, 16 Dec 2024 16:00:00 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description To: Inochi Amaoto Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yixun Lan , Longbin Li , Conor Dooley , Chen Wang , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Charlie Jenkins , Andrew Jones , Jesse Taube , Andy Chiu , Alexandre Ghiti , Yong-Xuan Wang References: <20241206055829.1059293-1-inochiama@gmail.com> <20241206055829.1059293-2-inochiama@gmail.com> From: Samuel Holland Content-Language: en-US In-Reply-To: <20241206055829.1059293-2-inochiama@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2024-12-05 11:58 PM, Inochi Amaoto wrote: > Add description for the BFloat16 precision Floating-Point ISA extension, > (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 > ("Added Chapter title to BF16") of the riscv-isa-manual. > > Signed-off-by: Inochi Amaoto > Acked-by: Conor Dooley > --- > .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 9c7dd7e75e0c..0a1f1a76d129 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -329,6 +329,12 @@ properties: > instructions, as ratified in commit 056b6ff ("Zfa is ratified") of > riscv-isa-manual. > > + - const: zfbfmin > + description: > + The standard Zfbfmin extension which provides minimal support for > + 16-bit half-precision brain floating-point instructions, as ratified I think you mean "binary" here and in the entries below, not "brain". > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > - const: zfh > description: > The standard Zfh extension for 16-bit half-precision binary > @@ -525,6 +531,18 @@ properties: > in commit 6f702a2 ("Vector extensions are now ratified") of > riscv-v-spec. > > + - const: zvfbfmin > + description: > + The standard Zvfbfmin extension for minimal support for vectored > + 16-bit half-precision brain floating-point instructions, as ratified > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > + - const: zvfbfwma > + description: > + The standard Zvfbfwma extension for vectored half-precision brain > + floating-point widening multiply-accumulate instructions, as ratified > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > - const: zvfh > description: > The standard Zvfh extension for vectored half-precision > @@ -663,6 +681,33 @@ properties: > then: > contains: > const: zca > + # Zfbfmin depends on F > + - if: > + contains: > + const: zfbfmin > + then: > + contains: > + const: f > + # Zvfbfmin depends on V or Zve32f > + - if: > + contains: > + const: zvfbfmin > + then: > + oneOf: > + - contains: > + const: v > + - contains: > + const: zve32f > + # Zvfbfwma depends on Zfbfmin and Zvfbfmin > + - if: > + contains: > + const: zvfbfwma > + then: > + allOf: > + - contains: > + const: zfbfmin > + - contains: > + const: zvfbfmin > > allOf: > # Zcf extension does not exist on rv64