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bh=Yfl/w1ij3MgpyEqu5acDmeSHKzp1JdcGMEvJsVUioeI=; b=dTapjwhlsakHuG9/ro3lz63N01 XdRqX6PAtHDsv/Hqx89CpF904TiwsjZnD8ckUY/929k3Kqh6zJWEV/bZwHUToTvKGf9yVJ6uGH3ls 8Kwrz9WhU0B/zKeitP6JlW0f7htpsvS6bhNBxQXHc1qf9f77rtkXHumMFFi0polKAmpE1zRkNzspa fHCxnwx+tD75qpHwxRukvdgbcqzqhSja9xlzKE8/AnrpaVpvoBqytXXymP5r5Ao7xRd6gc1mYVTR8 2QTy+ybeTSBCzaSl9bns7x65+O5sMF5eXEPOAWZiSq47yrUdD32xbkhLxziC+Rkra+/azUmpQMB6A ZJ/I/QVg==; Received: from d100-78.icpnet.pl ([77.65.100.78] helo=[192.168.0.120]) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1w7x8q-0000000Ajrx-2VZg; Wed, 01 Apr 2026 17:06:00 +0200 Message-ID: <5e9f5f0c-1ff0-4b6c-ad2d-ccf6fafbef30@szczodrzynski.pl> Date: Wed, 1 Apr 2026 17:04:48 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/6] drm/sun4i: Support LVDS on D1s/T113 combo D-PHY To: Parthiban , Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, paulk@sys-base.io References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> <20251116134609.447043-1-kuba@szczodrzynski.pl> <1027afd7-dec6-4ff3-85eb-2d9a1646ada6@linumiz.com> Content-Language: pl From: =?UTF-8?Q?Kuba_Szczodrzy=C5=84ski?= Autocrypt: addr=kuba@szczodrzynski.pl; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authenticated-Id: kuba@szczodrzynski.pl Hi, W dniu 2026-04-01 o 10:39:42, Parthiban pisze: > Dear Kuba, > > On 2/7/26 2:34 PM, Parthiban wrote: >> On 11/16/25 2:46 PM, Kuba Szczodrzyński wrote: >>> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo >>> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same >>> PD0..PD9 pins are used for either DSI or LVDS. >>> >>> Other than having to use the combo D-PHY, LVDS output is configured in >>> the same way as on older chips. >>> >>> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It >>> is then configured by the LCD TCON, which allows connecting a >>> single-link LVDS display panel. > Now I also have the MIPI and LVDS working together on A133. Can I pick your > changes and post a combined series for the display support for A133? This will > also address D1s/T114 as well. I guess it's been waiting for too long anyway - so yes, if you know how to push it further, then please do so. Regards Kuba > -- > Thanks, > Parthiban > https://linumiz.com > https://www.linkedin.com/company/linumiz