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From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "Shawn Sung (宋孝謙)" <Shawn.Sung@mediatek.com>,
	"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
	"angelogioacchino.delregno@collabora.com"
	<angelogioacchino.delregno@collabora.com>
Cc: "linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Bibby Hsieh (謝濟遠)" <Bibby.Hsieh@mediatek.com>,
	"jason-ch.chen@mediatek.corp-partner.google.com"
	<jason-ch.chen@mediatek.corp-partner.google.com>,
	"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
	"daniel@ffwll.ch" <daniel@ffwll.ch>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"airlied@gmail.com" <airlied@gmail.com>,
	"sean@poorly.run" <sean@poorly.run>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"fshao@chromium.org" <fshao@chromium.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v7 11/18] drm/mediatek: Support "Pre-multiplied" blending in OVL
Date: Fri, 3 May 2024 09:04:14 +0000	[thread overview]
Message-ID: <5ebb2b0af6d26ee3137b2716f7068acf8233b80a.camel@mediatek.com> (raw)
In-Reply-To: <20240502103848.5845-12-shawn.sung@mediatek.com>

Hi, Shawn:

On Thu, 2024-05-02 at 18:38 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> Support "Pre-multiplied" alpha blending mode on in OVL.
> Before this patch, only the "coverage" mode is supported.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 +++++++++++++++++++++
> ----
>  1 file changed, 35 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index e41fd83e36e79..ad84c2fe57111 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -52,13 +52,16 @@
>  #define GMC_THRESHOLD_HIGH	((1 << GMC_THRESHOLD_BITS) / 4)
>  #define GMC_THRESHOLD_LOW	((1 << GMC_THRESHOLD_BITS) / 8)
>  
> +#define OVL_CON_CLRFMT_MAN	BIT(23)
>  #define OVL_CON_BYTE_SWAP	BIT(24)
> -#define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
> +#define OVL_CON_RGB_SWAP	BIT(25)
>  #define OVL_CON_CLRFMT_RGB	(1 << 12)
>  #define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
>  #define OVL_CON_CLRFMT_ARGB8888	(3 << 12)
>  #define OVL_CON_CLRFMT_UYVY	(4 << 12)
>  #define OVL_CON_CLRFMT_YUYV	(5 << 12)
> +#define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
> +#define OVL_CON_CLRFMT_PARGB8888	(OVL_CON_CLRFMT_ARGB8888 |
> OVL_CON_CLRFMT_MAN)
>  #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ?
> \
>  					0 : OVL_CON_CLRFMT_RGB)
>  #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ?
> \
> @@ -72,6 +75,8 @@
>  #define	OVL_CON_VIRT_FLIP	BIT(9)
>  #define	OVL_CON_HORZ_FLIP	BIT(10)
>  
> +#define OVL_COLOR_ALPHA		GENMASK(31, 24)
> +
>  static inline bool is_10bit_rgb(u32 fmt)
>  {
>  	switch (fmt) {
> @@ -296,7 +301,13 @@ void mtk_ovl_config(struct device *dev, unsigned
> int w,
>  	if (w != 0 && h != 0)
>  		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl-
> >cmdq_reg, ovl->regs,
>  				      DISP_REG_OVL_ROI_SIZE);
> -	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, 
> DISP_REG_OVL_ROI_BGCLR);
> +
> +	/*
> +	 * The background color must be opaque black (ARGB),
> +	 * otherwise the alpha blending will have no effect
> +	 */
> +	mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl-
> >cmdq_reg,
> +			      ovl->regs, DISP_REG_OVL_ROI_BGCLR);
>  
>  	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_RST);
>  	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_RST);
> @@ -372,7 +383,8 @@ void mtk_ovl_layer_off(struct device *dev,
> unsigned int idx,
>  		      DISP_REG_OVL_RDMA_CTRL(idx));
>  }
>  
> -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> unsigned int fmt)
> +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> unsigned int fmt,
> +				    unsigned int blend_mode)
>  {
>  	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
>  	 * is defined in mediatek HW data sheet.
> @@ -391,21 +403,35 @@ static unsigned int ovl_fmt_convert(struct
> mtk_disp_ovl *ovl, unsigned int fmt)
>  		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
>  	case DRM_FORMAT_RGBX8888:
>  	case DRM_FORMAT_RGBA8888:
> +		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> +		       OVL_CON_CLRFMT_ARGB8888 :
> +		       OVL_CON_CLRFMT_PARGB8888;
>  	case DRM_FORMAT_RGBX1010102:
>  	case DRM_FORMAT_RGBA1010102:
>  		return OVL_CON_CLRFMT_ARGB8888;
>  	case DRM_FORMAT_BGRX8888:
>  	case DRM_FORMAT_BGRA8888:
> +		return OVL_CON_BYTE_SWAP |
> +		       (blend_mode == DRM_MODE_BLEND_COVERAGE ?
> +		       OVL_CON_CLRFMT_ARGB8888 :
> +		       OVL_CON_CLRFMT_PARGB8888);
>  	case DRM_FORMAT_BGRX1010102:
>  	case DRM_FORMAT_BGRA1010102:
>  		return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
>  	case DRM_FORMAT_XRGB8888:
>  	case DRM_FORMAT_ARGB8888:
> +		return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> +		       OVL_CON_CLRFMT_RGBA8888 :
> +		       OVL_CON_CLRFMT_PARGB8888;
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_ARGB2101010:
>  		return OVL_CON_CLRFMT_RGBA8888;
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ABGR8888:
> +		return OVL_CON_RGB_SWAP |
> +		       (blend_mode == DRM_MODE_BLEND_COVERAGE ?
> +		       OVL_CON_CLRFMT_RGBA8888 :
> +		       OVL_CON_CLRFMT_PARGB8888);

Originally when coverage mode, XBGR8888 and ABGR8888 return

OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP

but this patch return 

OVL_CON_CLRFMT_RGBA8888 | OVL_CON_RGB_SWAP

This modification is not related to pre-multiplied blending, so
separate to another patch.


>  	case DRM_FORMAT_XBGR2101010:
>  	case DRM_FORMAT_ABGR2101010:
>  		return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
> @@ -429,6 +455,7 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  	unsigned int fmt = pending->format;
>  	unsigned int offset = (pending->y << 16) | pending->x;
>  	unsigned int src_size = (pending->height << 16) | pending-
> >width;
> +	unsigned int blend_mode = state->base.pixel_blend_mode;
>  	unsigned int ignore_pixel_alpha = 0;
>  	unsigned int con;
>  	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
> @@ -447,9 +474,11 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  		return;
>  	}
>  
> -	con = ovl_fmt_convert(ovl, fmt);
> -	if (state->base.fb && state->base.fb->format->has_alpha)
> -		con |= OVL_CON_AEN | OVL_CON_ALPHA;
> +	con = ovl_fmt_convert(ovl, fmt, blend_mode);
> +	if (state->base.fb) {
> +		con |= OVL_CON_AEN;
> +		con |= state->base.alpha & OVL_CON_ALPHA;

This looks like plane alpha (The whole video plane use single alpha
value), not related to pre-multiplied blending. So separate to another
patch.

Regards,
CK

> +	}
>  
>  	if (state->base.fb && !state->base.fb->format->has_alpha)
>  		ignore_pixel_alpha = OVL_CONST_BLEND;

  reply	other threads:[~2024-05-03  9:04 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-02 10:38 [PATCH v7 00/18] Support IGT in display driver Shawn Sung
2024-05-02 10:38 ` [PATCH v7 01/18] soc: mediatek: Disable 9-bit alpha in ETHDR Shawn Sung
2024-05-07  5:58   ` CK Hu (胡俊光)
2024-05-07 10:02     ` Shawn Sung (宋孝謙)
2024-05-02 10:38 ` [PATCH v7 02/18] drm/mediatek: Add OVL compatible name for MT8195 Shawn Sung
2024-05-02 10:38 ` [PATCH v7 03/18] drm/mediatek: Add missing plane settings when async update Shawn Sung
2024-05-02 10:38 ` [PATCH v7 04/18] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Shawn Sung
2024-05-02 10:38 ` [PATCH v7 05/18] drm/mediatek: Set DRM mode configs accordingly Shawn Sung
2024-05-03  2:38   ` CK Hu (胡俊光)
2024-05-27  4:33   ` Fei Shao
2024-05-27  4:38     ` Chen-Yu Tsai
2024-05-27  4:54       ` Fei Shao
2024-05-27  5:28         ` Chen-Yu Tsai
2024-05-02 10:38 ` [PATCH v7 06/18] drm/mediatek: Turn off the layers with zero width or height Shawn Sung
2024-05-02 10:38 ` [PATCH v7 07/18] drm/mediatek: Support more 10bit formats in OVL Shawn Sung
2024-05-03  2:51   ` CK Hu (胡俊光)
2024-05-02 10:38 ` [PATCH v7 08/18] drm/mediatek: Support RGBA8888 and RGBX8888 " Shawn Sung
2024-05-03  2:58   ` CK Hu (胡俊光)
2024-05-02 10:38 ` [PATCH v7 09/18] drm/mediatek: Support constant blending " Shawn Sung
2024-05-03  5:29   ` CK Hu (胡俊光)
2024-05-03  5:52   ` CK Hu (胡俊光)
2024-05-02 10:38 ` [PATCH v7 10/18] drm/mediatek: Support constant blending in Mixer Shawn Sung
2024-05-03  5:45   ` CK Hu (胡俊光)
2024-05-02 10:38 ` [PATCH v7 11/18] drm/mediatek: Support "Pre-multiplied" blending in OVL Shawn Sung
2024-05-03  9:04   ` CK Hu (胡俊光) [this message]
2024-05-02 10:38 ` [PATCH v7 12/18] drm/mediatek: Support "Pre-multiplied" blending in Mixer Shawn Sung
2024-05-03  9:28   ` CK Hu (胡俊光)
2024-05-02 10:38 ` [PATCH v7 13/18] drm/mediatek: Support "None" blending in OVL Shawn Sung
2024-05-02 10:38 ` [PATCH v7 14/18] drm/mediatek: Support "None" blending in Mixer Shawn Sung
2024-05-03  9:40   ` CK Hu (胡俊光)
2024-05-02 10:38 ` [PATCH v7 15/18] drm/mediatek: Support alpha blending in display driver Shawn Sung
2024-05-02 10:38 ` [PATCH v7 16/18] drm/mediatek: Support CRC " Shawn Sung
2024-05-04 14:22   ` kernel test robot
2024-05-02 10:38 ` [PATCH v7 17/18] drm/mediatek: Support CRC in OVL Shawn Sung
2024-05-02 10:38 ` [PATCH v7 18/18] drm/mediatek: Support CRC in OVL adaptor Shawn Sung

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