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Wed, 9 Apr 2025 01:41:43 +0000 Message-ID: <5ece1b6b-a225-4fab-be74-b48037986686@intel.com> Date: Tue, 8 Apr 2025 18:41:40 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/7] Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) To: "Moger, Babu" , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , References: <7c135464-d859-459b-b86d-e8c18f106fc4@intel.com> <251c8fe1-603f-4993-a822-afb35b49cdfa@amd.com> <4a98eccf-4d31-40ac-8112-c89cde7a1c6e@intel.com> <46e40771-c73c-4ceb-acc3-812693f98f19@amd.com> From: Reinette Chatre Content-Language: en-US In-Reply-To: <46e40771-c73c-4ceb-acc3-812693f98f19@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: MW4PR04CA0243.namprd04.prod.outlook.com (2603:10b6:303:88::8) To SJ2PR11MB7573.namprd11.prod.outlook.com (2603:10b6:a03:4d2::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR11MB7573:EE_|CYXPR11MB8664:EE_ X-MS-Office365-Filtering-Correlation-Id: 4607d849-300d-4949-7ef7-08dd7707ae45 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014; 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According >>>> to APM: >>>>     Depending on the implementation, some portions of the L3 Cache may be >>>>     shared by other system functions or used for some other purpose not >>>>     under the control of the PQOS feature set. The L3 Cache Allocation >>>>     Sharing Mask returned by CPUID Fn0000_0010_EBX_x1[L3ShareAllocMask] is a >>>>     bitmask that represents portions of the L3 that may be shared by those >>>>     functions. >>> >>> Here is the complete text. >>> >>> The L3 Cache allocation sharing mask (L3ShareAllocMask) returned in EBX by >>> CPUID Fn0000_0010 with ECX=1 is a bit vector which represents portions of >>> the cache which may be shared with other system entities or used for some >>> other purpose not under the control of the QOS feature set. When software >>> sets a bit in one of the L3_MASK_n registers at the same bit positions a >>> bit in the L3ShareAllocMask, processors executing with the corresponding >>> COS will competitively share that portion of the cache with the other >>> function. If this mask is all 0’s, then there is no other entity in the >>> system competing with the processors for use of the L3 cache. >>> >>> The "L3ShareAllocMask" is always reported as 0 on AMD systems. >>> >>>> Could you please include what (if any) the relationship is between the CBM >>>> discoverable via Fn0000_0010_EBX_x1[L3ShareAllocMask] and the CBM of >>>> "highest-supported L3_MASK_n register" when SDCIAE is enabled? >>> >>> No. There is no relationship in here. >>> >>>> >>>> On the resctrl interface side the documentation currently states: >>>> >>>>     "shareable_bits": >>>>         Bitmask of shareable resource with other executing >>>>         entities (e.g. I/O). User can use this when >>>>         setting up exclusive cache partitions. Note that >>>>         some platforms support devices that have their >>>>         own settings for cache use which can over-ride >>>>         these bits. >>>> >>>> Even though this was originally used to expose the content of >>>> Fn0000_0010_EBX_x1[L3ShareAllocMask] the intent of the content does >>>> seem to also apply to the "io_alloc" CBM also. >>> >>> It says "shared by other system functions or used for some other purpose >>> not under the control of the PQOS feature set". >> >> This is a quote from the AMD spec, not the resctrl user interface documentation. >> >> Please consider this from resctrl user interface perspective. >> >>> >>> "io_alloc" is PQOS feature set. I feel it should not affect "shareable_bits". >> >> When I read the resctrl user interface documentation for "shareable_bits" it >> sounds relevant to io_alloc. The "shareable_bits" contains a bitmask "of >> shareable resource with other executing entities (e.g. I/O)" ... is this >> not exactly io_alloc? > > I agree the text is pretty generic. Actually, the whole bit mask (0xfffF) is shareable with io_alloc. I think the value of "shareable_bits" presented to user space could be the actual io_alloc_cbm value. Thus, not the "possible IO bitmask" but the actual value. This seems to be the best match of what "shareable_bits" represents, which is the region currently used by IO devices. This partners well with the "bit_usage" output, for example, "X" can be used to show which portions of cache are currently used by both software (via schemata of resource groups) and hardware (via io_alloc_cbm). > > The 'shareable_bits' is coming from CPUID Fn0000_0010_EBX_x1[L3ShareAllocMask] which is always 0 on AMD systems. > It will be bit odd to manipulate these value. Not sure if we have to do it. It is not clear to me what you mean with "manipulate". "shareable_bits" does currently come from the existing register but AMD now provides more interfaces with which this data can be obtained and it seems appropriate to use it. Reinette