From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: "Colin Ian King" <colin.i.king@gmail.com>,
"Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
Xinhui.Pan@amd.com, "David Airlie" <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: kernel-janitors@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] drm/amd/display: Fix spelling mistake: "dram_clk_chanage" -> "dram_clk_change"
Date: Thu, 8 Dec 2022 10:43:12 -0500 [thread overview]
Message-ID: <5f1c3233-2b39-39a5-24d1-d0bbead4ed65@amd.com> (raw)
In-Reply-To: <20221208121854.2436398-1-colin.i.king@gmail.com>
On 12/8/22 07:18, Colin Ian King wrote:
> There is a spelling mistake in the struct field dram_clk_chanage. Fix it.
>
> Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Applied. Thanks!
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 8 ++++----
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 4 ++--
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 8 ++++----
> drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 8 ++++----
> drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 8 ++++----
> drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 +-
> 7 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> index 0f746bb4e500..d51f1ce02874 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
> @@ -55,7 +55,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
>
> s = &wm->sets[1];
> s->wm_set = 1;
> @@ -65,7 +65,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
>
> s = &wm->sets[2];
> s->wm_set = 2;
> @@ -75,7 +75,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
>
> s = &wm->sets[3];
> s->wm_set = 3;
> @@ -85,7 +85,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
> }
>
> void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index c8ec11839b4d..fe2023f18b7d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -159,7 +159,7 @@ static void dcn10_log_hubbub_state(struct dc *dc,
> DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
> DTN_INFO_MICRO_SEC(s->sr_enter);
> DTN_INFO_MICRO_SEC(s->sr_exit);
> - DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
> + DTN_INFO_MICRO_SEC(s->dram_clk_change);
> DTN_INFO("\n");
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> index e8b6065fffad..a0f8e31d2adc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> @@ -83,7 +83,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i
> memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
> dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
>
> - chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n");
> + chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_change\n");
> remaining_buffer -= chars_printed;
> pBuf += chars_printed;
>
> @@ -98,7 +98,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i
> (s->pte_meta_urgent * frac) / ref_clk_mhz / frac, (s->pte_meta_urgent * frac) / ref_clk_mhz % frac,
> (s->sr_enter * frac) / ref_clk_mhz / frac, (s->sr_enter * frac) / ref_clk_mhz % frac,
> (s->sr_exit * frac) / ref_clk_mhz / frac, (s->sr_exit * frac) / ref_clk_mhz % frac,
> - (s->dram_clk_chanage * frac) / ref_clk_mhz / frac, (s->dram_clk_chanage * frac) / ref_clk_mhz % frac);
> + (s->dram_clk_change * frac) / ref_clk_mhz / frac, (s->dram_clk_change * frac) / ref_clk_mhz % frac);
> remaining_buffer -= chars_printed;
> pBuf += chars_printed;
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
> index aacb1fb5c73e..24bd93219936 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
> @@ -500,7 +500,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
>
> s = &wm->sets[1];
> s->wm_set = 1;
> @@ -511,7 +511,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
>
> s = &wm->sets[2];
> s->wm_set = 2;
> @@ -522,7 +522,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
>
> s = &wm->sets[3];
> s->wm_set = 3;
> @@ -533,7 +533,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
> s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
> s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
> }
> - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
> + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
> }
>
> void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
> index c5e200d09038..aeb0e0d9b70a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
> @@ -635,7 +635,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,
> - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_change);
>
> s = &wm->sets[1];
> s->wm_set = 1;
> @@ -649,7 +649,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,
> - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_change);
>
> s = &wm->sets[2];
> s->wm_set = 2;
> @@ -663,7 +663,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C,
> - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_change);
>
> s = &wm->sets[3];
> s->wm_set = 3;
> @@ -677,7 +677,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D,
> - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_change);
> }
>
> static void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
> index 5947c2cb0f30..9501403a48a9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
> @@ -865,7 +865,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
> - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_change);
>
> REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
> DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain);
> @@ -885,7 +885,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
> - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_change);
>
> REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
> DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain);
> @@ -905,7 +905,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
> - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_change);
>
> REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
> DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain);
> @@ -925,7 +925,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
> DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
>
> REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
> - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
> + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_change);
>
> REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
> DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain);
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
> index f2e1fcb668fb..5b0265c0df61 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
> @@ -46,7 +46,7 @@ struct dcn_hubbub_wm_set {
> uint32_t pte_meta_urgent;
> uint32_t sr_enter;
> uint32_t sr_exit;
> - uint32_t dram_clk_chanage;
> + uint32_t dram_clk_change;
> uint32_t usr_retrain;
> uint32_t fclk_pstate_change;
> };
--
Hamza
prev parent reply other threads:[~2022-12-08 15:42 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-08 12:18 Colin Ian King
2022-12-08 15:43 ` Hamza Mahfooz [this message]
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