From: "Maíra Canal" <mcanal@igalia.com>
To: Daniel Almeida <daniel.almeida@collabora.com>
Cc: "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
"Danilo Krummrich" <dakr@kernel.org>,
"Daniel Stone" <daniels@collabora.com>,
"Rob Herring" <robh@kernel.org>,
"Alice Ryhl" <alice.ryhl@google.com>,
"Beata Michalska" <beata.michalska@arm.com>,
"Carsten Haitzler" <carsten.haitzler@foss.arm.com>,
"Boris Brezillon" <boris.brezillon@collabora.com>,
"Ashley Smith" <ashley.smith@collabora.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, kernel@collabora.com
Subject: Re: [PATCH] Introduce Tyr
Date: Thu, 3 Jul 2025 07:45:56 -0300 [thread overview]
Message-ID: <5f28693f-a181-485a-aee7-38c5212bdea1@igalia.com> (raw)
In-Reply-To: <C2A539D0-8C07-44A4-93AD-21343396D84F@collabora.com>
Hi Daniel,
On 30/06/25 10:53, Daniel Almeida wrote:
> Hi Maíra, thanks for chiming in :)
>
>>
>> To enhance readability, consider using a regmap similar to
>> panthor_regs.h. This would help avoid 'magic numbers' and make the
>> code's intent much clearer.
>
>
> Are you referring to "struct regmap" itself? Because last I checked, this
> abstraction is not available upstream. There was a person working on it, but I
> guess it hasn't seen any traction for a few months. I also don't see it being
> used in panthor_regs.h?
Sorry, I think I didn't express myself clearly. When I say regmap, I
mean using macros to express the register addresses and its fields. From
example, in Panthor, "1 | bit_u32(8)" is expressed as
GPU_IRQ_RESET_COMPLETED, which can make things more readable.
Best Regards,
- Maíra
>
>>
>>> + regs::GPU_CMD.write(iomem, irq_enable_cmd)?;
>>> +
>>> + let op = || regs::GPU_INT_RAWSTAT.read(iomem);
>>> + let cond = |raw_stat: &u32| -> bool { (*raw_stat >> 8) & 1 == 1 };
>>> + let res = io::poll::read_poll_timeout(
>>> + op,
>>> + cond,
>>> + time::Delta::from_millis(100),
>>> + Some(time::Delta::from_micros(20000)),
>>> + );
>>> +
>>> + if let Err(e) = res {
>>> + pr_err!("GPU reset failed with errno {}\n", e.to_errno());
>>> + pr_err!(
>>> + "GPU_INT_RAWSTAT is {}\n",
>>> + regs::GPU_INT_RAWSTAT.read(iomem)?
>>> + );
>>> + }
>>> +
>>> + Ok(())
>>> +}
>>> +
>>> +kernel::of_device_table!(
>>> + OF_TABLE,
>>> + MODULE_OF_TABLE,
>>> + <TyrDriver as platform::Driver>::IdInfo,
>>> + [
>>> + (of::DeviceId::new(c_str!("rockchip,rk3588-mali")), ()),
>>> + (of::DeviceId::new(c_str!("arm,mali-valhall-csf")), ())
>>> + ]
>>> +);
>>> +
>>> +impl platform::Driver for TyrDriver {
>>> + type IdInfo = ();
>>> + const OF_ID_TABLE: Option<of::IdTable<Self::IdInfo>> = Some(&OF_TABLE);
>>> +
>>> + fn probe(
>>> + pdev: &platform::Device<Core>,
>>> + _info: Option<&Self::IdInfo>,
>>> + ) -> Result<Pin<KBox<Self>>> {
>>> + dev_dbg!(pdev.as_ref(), "Probed Tyr\n");
>>> +
>>> + let core_clk = Clk::get(pdev.as_ref(), Some(c_str!("core")))?;
>>> + let stacks_clk = Clk::get(pdev.as_ref(), Some(c_str!("stacks")))?;
>>
>> Shouldn't it be OptionalClk::get? From the DT schema for "arm,mali-
>> valhall-csf", I see that "stacks" and "coregroups" are optional.
>>
>>> + let coregroup_clk = Clk::get(pdev.as_ref(), Some(c_str!("coregroup")))?;
>>
>> Same.
>>
>> Best Regards,
>> - Maíra
>>
>>
>
> Ah yes, you’re right. I will fix that in v2.
>
> — Daniel
>
next prev parent reply other threads:[~2025-07-03 10:46 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-27 22:34 Daniel Almeida
2025-06-27 22:36 ` Daniel Almeida
2025-06-27 22:39 ` Boqun Feng
2025-06-27 22:56 ` Boqun Feng
2025-06-27 23:12 ` Danilo Krummrich
2025-06-28 0:12 ` Daniel Almeida
2025-06-28 9:31 ` Miguel Ojeda
2025-06-30 13:52 ` Rob Herring
2025-06-30 14:01 ` Daniel Almeida
2025-06-30 17:29 ` Miguel Ojeda
2025-06-30 16:06 ` Boris Brezillon
2025-06-30 16:12 ` Danilo Krummrich
2025-07-01 9:11 ` Boris Brezillon
2025-06-28 9:44 ` Miguel Ojeda
2025-06-28 13:05 ` Daniel Almeida
2025-06-28 13:49 ` FUJITA Tomonori
2025-06-28 14:29 ` Miguel Ojeda
2025-06-30 15:22 ` Daniel Almeida
2025-06-30 17:29 ` Miguel Ojeda
2025-06-28 19:55 ` Maíra Canal
2025-06-30 13:53 ` Daniel Almeida
2025-07-03 10:45 ` Maíra Canal [this message]
2025-06-30 10:11 ` Steven Price
2025-06-30 14:56 ` Daniel Almeida
2025-06-30 15:31 ` Steven Price
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